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Design of Low Power FlipFlop to Reduce Area and Delay using Conditional Pulse Enhancement Method

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IJCA Special Issue on International Conference on Electronics, Communication and Information systems
© 2012 by IJCA Journal
ICECI - Number 2
Year of Publication: 2012
Authors:
G. Venkadeshkumar
K. Pandiaraj

G Venkadeshkumar and K Pandiaraj. Article: Design of Low Power FlipFlop to Reduce Area and Delay using Conditional Pulse Enhancement Method. IJCA Special Issue on International Conference on Electronics, Communication and Information systems ICECI(2):25-28, November 2012. Full text available. BibTeX

@article{key:article,
	author = {G. Venkadeshkumar and K. Pandiaraj},
	title = {Article: Design of Low Power FlipFlop to Reduce Area and Delay using Conditional Pulse Enhancement Method},
	journal = {IJCA Special Issue on International Conference on Electronics, Communication and Information systems},
	year = {2012},
	volume = {ICECI},
	number = {2},
	pages = {25-28},
	month = {November},
	note = {Full text available}
}

Abstract

A low power pulse triggered ?ip?op (P-FF) design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. A conditional pulse enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse generation circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 90-nm technology reveal that the enhanced pulse triggered FF design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38. 4%. Compared with the conventional transmission gate based flipflop design. The average leakage power consumption is also reduced by a factor of 3. 52.

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