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Fault Secure Memory Design using Difference Set Codes

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IJCA Special Issue on International Conference on Electronics, Communication and Information systems
© 2012 by IJCA Journal
ICECI - Number 2
Year of Publication: 2012
Authors:
K. Manikandan
G. Thiruselvi

K Manikandan and G Thiruselvi. Article: Fault Secure Memory Design using Difference Set Codes. IJCA Special Issue on International Conference on Electronics, Communication and Information systems ICECI(2):29-32, November 2012. Full text available. BibTeX

@article{key:article,
	author = {K. Manikandan and G. Thiruselvi},
	title = {Article: Fault Secure Memory Design using Difference Set Codes},
	journal = {IJCA Special Issue on International Conference on Electronics, Communication and Information systems},
	year = {2012},
	volume = {ICECI},
	number = {2},
	pages = {29-32},
	month = {November},
	note = {Full text available}
}

Abstract

Modified decoding algorithms for DS codes are proposed that, in addition to error correction, provide error detection when the number of correctable bit errors is exceeded by one. This combined error detection and correction capability of the modified decoder are provide to prevent soft errors from causing data corruption, memories are typically protected with error correction codes (ECCs). Memory applications require low latency encoders and decoders. These codes allow us to design a fault tolerant error-detector unit that detects any error in the received code-vector despite having faults in the detector circuitry. The fault secure detector unit to check the output vector of the encoder and corrector circuitry, and if there is any error in the output of either of these units, that unit has to redo the operation to generate the correct output vector. Using this detect-and-repeat technique, correct potential transient errors in the encoder or corrector output and provide fault tolerant memory system with fault-tolerant supporting circuitry.

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