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Reduction of Hardware Complexity and Truncation Error by using Fixed Width Baugh Wooley Multiplier

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IJCA Special Issue on International Conference on Electronics, Communication and Information systems
© 2012 by IJCA Journal
ICECI - Number 3
Year of Publication: 2012
Authors:
P. Arun Pandian
T. Vijaya Bharathi

Arun P Pandian and Vijaya T Bharathi. Article: Reduction of Hardware Complexity and Truncation Error by using Fixed Width Baugh Wooley Multiplier. IJCA Special Issue on International Conference on Electronics, Communication and Information systems ICECI(3):10-13, November 2012. Full text available. BibTeX

@article{key:article,
	author = {P. Arun Pandian and T. Vijaya Bharathi},
	title = {Article: Reduction of Hardware Complexity and Truncation Error by using Fixed Width Baugh Wooley Multiplier},
	journal = {IJCA Special Issue on International Conference on Electronics, Communication and Information systems},
	year = {2012},
	volume = {ICECI},
	number = {3},
	pages = {10-13},
	month = {November},
	note = {Full text available}
}

Abstract

The fixed-width multiplier is attractive to many multimedia and digital signal processing systems which are desirable to maintain a fixed format and allow a little accuracy loss to output data. In this paper, we propose a new error compensation circuit in Baugh-Wooley multiplier by using the dual group minor input correction (MIC) vector to lower input correction vector compensation error. By constructing the error compensation circuit mainly from the "outer" partial products, the hardware complexity only increases slightly as the multiplier input bits increase. In the proposed 16 *16 bits fixed-width multiplier, the truncation error can be lowered by compared with the direct-truncated multiplier and the transistor count can be reduced by compared with the full-length multiplier.

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