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Reseach Article

Power Reduction Technique in LFSR using Modified Control Logic for VLSI Circuit

Published on February 2013 by Praveen J, M N Shanmukhaswamy
International Conference on Electronic Design and Signal Processing
Foundation of Computer Science USA
ICEDSP - Number 4
February 2013
Authors: Praveen J, M N Shanmukhaswamy
4d1181a1-3424-4f00-bc36-3aa5316d9f6b

Praveen J, M N Shanmukhaswamy . Power Reduction Technique in LFSR using Modified Control Logic for VLSI Circuit. International Conference on Electronic Design and Signal Processing. ICEDSP, 4 (February 2013), 21-24.

@article{
author = { Praveen J, M N Shanmukhaswamy },
title = { Power Reduction Technique in LFSR using Modified Control Logic for VLSI Circuit },
journal = { International Conference on Electronic Design and Signal Processing },
issue_date = { February 2013 },
volume = { ICEDSP },
number = { 4 },
month = { February },
year = { 2013 },
issn = 0975-8887,
pages = { 21-24 },
numpages = 4,
url = { /specialissues/icedsp/number4/10372-1031/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 International Conference on Electronic Design and Signal Processing
%A Praveen J
%A M N Shanmukhaswamy
%T Power Reduction Technique in LFSR using Modified Control Logic for VLSI Circuit
%J International Conference on Electronic Design and Signal Processing
%@ 0975-8887
%V ICEDSP
%N 4
%P 21-24
%D 2013
%I International Journal of Computer Applications
Abstract

A linear feedback shift register (LFSR) is proposed technique which targets to reduce the power consumption within BIST itself. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage, Control Logic (CL) makes the clocks of the switching units of the register inactive for a time period when output from them is going to be same as previous one and thus reducing unnecessary switching of the flip-flops. And at second stage, the LFSR reorders the test vectors by interchanging the bit with its next and closest neighbor bit. It keeps fault coverage capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power while shifting operation.

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Index Terms

Computer Science
Information Sciences

Keywords

Built-in Self-test Vlsi Testing Low-power Test Vector Pattern Generation