The week's pick
Reseach Article
Reconfigurable Network on Chip Router for Image Processing Based Multiprocessor Applications
| International Conference on Electronics, Information and Communication Engineering |
| Foundation of Computer Science USA |
| ICEICE - Number 1 |
| December 2011 |
| Authors: Jonathan Joshi, Om Prakash Vyas, Sanjay Gaur |
| a0749c30-136d-495e-8306-e211da6ff56f |
Jonathan Joshi, Om Prakash Vyas, Sanjay Gaur . Reconfigurable Network on Chip Router for Image Processing Based Multiprocessor Applications. International Conference on Electronics, Information and Communication Engineering. ICEICE, 1 (December 2011), 8-11.
Abstract
Real time Image processing (I.P.) systems, involving on board multiprocessor communication, use standard bus based communication. The load on the system to deliver the output towards real time standards call for high speeds , but for data intensive application such as IP algorithms require constant transfer of data between the logic cores. This would need either dedicated connections or additional bus controllers. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of a bus-based solution. This paper deals with the design and implementation of a NoC router targeted for an Image processing system consisting of different modules. All the cores have been designed targeting real time frame rates. The design has been prototyped on a Virtex II FPGA. The timings are given in comparison to a standard DMA controller.
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