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Reseach Article

Optimum Body Biasing Technique in Domino Logic Gate Design for Low Power Applications

Published on December 2011 by Prof. B. P. Singh, Suman Nehra, K. G. Sharma, Tripti Sharma
International Conference on Electronics, Information and Communication Engineering
Foundation of Computer Science USA
ICEICE - Number 2
December 2011
Authors: Prof. B. P. Singh, Suman Nehra, K. G. Sharma, Tripti Sharma
4a8702d4-5c95-4c5e-9492-a0270db0e42c

Prof. B. P. Singh, Suman Nehra, K. G. Sharma, Tripti Sharma . Optimum Body Biasing Technique in Domino Logic Gate Design for Low Power Applications. International Conference on Electronics, Information and Communication Engineering. ICEICE, 2 (December 2011), 15-18.

@article{
author = { Prof. B. P. Singh, Suman Nehra, K. G. Sharma, Tripti Sharma },
title = { Optimum Body Biasing Technique in Domino Logic Gate Design for Low Power Applications },
journal = { International Conference on Electronics, Information and Communication Engineering },
issue_date = { December 2011 },
volume = { ICEICE },
number = { 2 },
month = { December },
year = { 2011 },
issn = 0975-8887,
pages = { 15-18 },
numpages = 4,
url = { /specialissues/iceice/number2/4259-iceice013/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 International Conference on Electronics, Information and Communication Engineering
%A Prof. B. P. Singh
%A Suman Nehra
%A K. G. Sharma
%A Tripti Sharma
%T Optimum Body Biasing Technique in Domino Logic Gate Design for Low Power Applications
%J International Conference on Electronics, Information and Communication Engineering
%@ 0975-8887
%V ICEICE
%N 2
%P 15-18
%D 2011
%I International Journal of Computer Applications
Abstract

Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this paper, AND gates with different body biasing are compared taking power consumption and delay as parameters. The designs are tested in 32nm technology. The domino AND gate design with least power consumption, delay and power delay product is proposed.

References
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Index Terms

Computer Science
Information Sciences

Keywords

CMOS Subthreshold regoin Domino logic Dynamic power Substrate Biasing