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Network-on-Chip Design for High Performance Demanding Multimedia Application

IP Multimedia Communications
© 2011 by IJCA Journal
ISBN : 978-93-80864-99-3
Year of Publication: 2011
Naveen Choudhary
M. S. Gaur
V. Laxmi

Naveen Choudhary, M S Gaur and V Laxmi. Network-on-Chip Design for High Performance Demanding Multimedia Application. Special issues on IP Multimedia Communications (1):155-160, October 2011. Full text available. BibTeX

	author = {Naveen Choudhary and M. S. Gaur and V. Laxmi},
	title = {Network-on-Chip Design for High Performance Demanding Multimedia Application},
	journal = {Special issues on IP Multimedia Communications},
	month = {October},
	year = {2011},
	number = {1},
	pages = {155-160},
	note = {Full text available}


Systems-on-Chip architecture integrates several heterogeneous components on a single chip. A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead. Network-on-chip (NoC) is a new approach for communication infrastructure of Systems-on-Chip (SoC) design, which provides network based solution for on-chip communication. Networks on Chip can be designed in different ways, according to the network architecture and protocol choice. It is important to balance the communication needs across the different links to avoid congestion and hot spots especially for high performance multimedia application. Application specific irregular topology based Network on Chip design can cater to the need of High performance demanding multimedia application which are congestion and energy aware. To achieve the mentioned objectives, this paper proposed two NoC design methodologies. Statistical experimental results show significant savings in communication bandwidth and communication energy for the high performance demanding multimedia applications when compared to existing standard 2D-Mesh NoCs.


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