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Simulation of Image Encryption Using AES Algorithm

Computational Science - New Dimensions & Perspectives
© 2011 by IJCA Journal
Number 4 - Article 8
Year of Publication: 2011
Soumiya Rasheed

Mr.P.Karthigaikumar and Soumiya Rasheed. Simulation of Image Encryption Using AES Algorithm. IJCA Special Issue on Computational Science - New Dimensions & Perspectives (4):166–172, 2011. Full text available. BibTeX

	author = {Mr.P.Karthigaikumar and Soumiya Rasheed},
	title = {Simulation of Image Encryption Using AES Algorithm},
	journal = {IJCA Special Issue on Computational Science - New Dimensions & Perspectives},
	year = {2011},
	number = {4},
	pages = {166--172},
	note = {Full text available}


With the fast progression of data exchange in electronic way, information security is becoming more important in data storage and transmission. Because of widely using images in industrial process, it is important to protect the confidential image data from unauthorized access.This paper presents the design of a 128 bit encoder using AES Rijndael Algorithm for image encryption. The AES algorithm defined by the National Institute of Standard and Technology(NIST) of United States has been widely accepted. Optimized and Synthesizable VHDL code is developed for the implementation of 128- bit data encryption and process. Xilinx ISE9.2i software is used for synthesis.Timing simulation is performed to verify the functionality of the designed circuit.


  • Bruce schneier“Applied Cryptography” 2nd Edition published by John Wiley&SonsInc.
  • William stallings “Cryptography and Network Security” 3rd Edition published by Pearson Education Inc and Dorling Kindersley Publishing Inc.
  • M. Zeghid, M. Machhout, L. Khriji, A. Baganne, and R. Tourki “A Modified AES Based Algorithm for ImageEncryption” World Academy of Science, Engineering and Technology 27, 2007
  • Abdelfatah A. Yahya and Ayman M. Abdalla“A Shuffle Image-Encryption Algorithm”Department of Computer Science, Al-Zaytoonah University of Jordan, Journal of Computer Science 4 (12): 999- 1002, 2008
  • Xinmiao Zhang, Student Member,IEEE, and Keshab K. Parthi, Fellow, IEEE “High-Speed VLSI Architecture for AES Algorithm” IEEE Transactions on VLSI, Vol.12, No.19, September 2004
  • Alireza Hodjat, Student Member, IEEE, and Ingrid Verbauwhede, Senior Member, IEEE “Area- Throughput Trade-Offs for Fully Pipelined30 to 70 Gbits/s AES Processors” IEEE Transactions on Computers, Vol.55, no.4, April2006
  • Pawel Chodowiec and Kris Gaj “Very compact FPGA implementation of the AES Algorithm”,in Proc. Of Cryptographic hardware and embedded system workshop,pp.319-333,2003
  • F.Rodriguez-Henriquez,N.A Saquib and A. Diaz- Perez“4.2 Gbits/sec Single Chip FPGA implementation of the AES Algorithm”, ElectronicsLetters, Vol.39, No.15, pp.1115-1116,2003
  • N. Sklavos and O. Koufopavlou, Member, IEEE “Architectures and VLSI Implementations of the AESProposal Rijndael” IEEE Transactions on Computers, Vol. 51, No. 12, December2002.
  • J.Bhasker “ A VHDL Primer”.3rd Edition published by Pearson Education Inc and Dorling Kindersley Publishing Inc.
  • J. Elbirt, W. Yip, B. Chetwynd, and C. Paar. An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalist. presented at Proc.3rdAESConf.(AES3).[Online].Available:http://cs ml.
  • V. Fischer and M. Drutarovsky, “Two methods of Rijndael implementation in reconfigurable hardware,” in Proc. , pp. 77–92, CHES 2001, Paris, France,May 2001.
  • H. Kuo and I. Verbauwhede, “Architectural optimization for a 1.82 Gbits/sec VLSI implementation of the AES Rijndael algorithm,” in Proc. CHES 2001, pp. 51–64, Paris, France, May 2001.
  • M. McLoone and J. V. McCanny, “Rijndael FPGA implementation utilizing look-up tables,” in IEEEWorkshop on Signal Processing Systems, pp.349–360, Sept. 2001.