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A High-Throughput ASIC implementation of Configurable Advanced Encryption Standard (AES) Processor

Published on December 2011 by P. Saravanan, N. Renuka Devi, G. Swathi, Dr. P. Kalpana
Network Security and Cryptography
Foundation of Computer Science USA
NSC - Number 3
December 2011
Authors: P. Saravanan, N. Renuka Devi, G. Swathi, Dr. P. Kalpana
037d117b-f051-45f0-9033-17708432eea0

P. Saravanan, N. Renuka Devi, G. Swathi, Dr. P. Kalpana . A High-Throughput ASIC implementation of Configurable Advanced Encryption Standard (AES) Processor. Network Security and Cryptography. NSC, 3 (December 2011), 1-6.

@article{
author = { P. Saravanan, N. Renuka Devi, G. Swathi, Dr. P. Kalpana },
title = { A High-Throughput ASIC implementation of Configurable Advanced Encryption Standard (AES) Processor },
journal = { Network Security and Cryptography },
issue_date = { December 2011 },
volume = { NSC },
number = { 3 },
month = { December },
year = { 2011 },
issn = 0975-8887,
pages = { 1-6 },
numpages = 6,
url = { /specialissues/nsc/number3/4334-spe028t/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 Network Security and Cryptography
%A P. Saravanan
%A N. Renuka Devi
%A G. Swathi
%A Dr. P. Kalpana
%T A High-Throughput ASIC implementation of Configurable Advanced Encryption Standard (AES) Processor
%J Network Security and Cryptography
%@ 0975-8887
%V NSC
%N 3
%P 1-6
%D 2011
%I International Journal of Computer Applications
Abstract

This paper proposes the Application Specific Integrated Circuit (ASIC) implementation of Advanced Encryption Standard (AES) cryptographic algorithm with reconfigurable 128-bit, 192-bit, 256-bit keys. The proposed implementation has compact 32-bit I/O for both data and key transfer. By using on the fly key generation for encryption process along with efficient implementation of MixColumn and InverseMixColumn operations using finite field GF(22) for our 32-bit AES crypto system gives a maximum of 80.1% improvement in operating frequency when compared to the recent implementations. The maximum operating frequency of our proposed pipelined implementation is 333 MHz with high throughput of around 10.656 Gbps in 180 nm standard cell CMOS technology.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Keywords - AES Cryptography Galois Field GF(28) On the fly key generation Throughput