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Reseach Article

Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks

Published on February 2012 by Naveen Choudhary, Dharm Singh, Abhilasha Sharma
Optimization and On-chip Communication
Foundation of Computer Science USA
OOC - Number 1
February 2012
Authors: Naveen Choudhary, Dharm Singh, Abhilasha Sharma
63ebbe65-a59d-4296-9d15-010c63f1b6e3

Naveen Choudhary, Dharm Singh, Abhilasha Sharma . Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks. Optimization and On-chip Communication. OOC, 1 (February 2012), 6-10.

@article{
author = { Naveen Choudhary, Dharm Singh, Abhilasha Sharma },
title = { Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks },
journal = { Optimization and On-chip Communication },
issue_date = { February 2012 },
volume = { OOC },
number = { 1 },
month = { February },
year = { 2012 },
issn = 0975-8887,
pages = { 6-10 },
numpages = 5,
url = { /specialissues/ooc/number1/5464-1002/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 Optimization and On-chip Communication
%A Naveen Choudhary
%A Dharm Singh
%A Abhilasha Sharma
%T Performance Evaluation of Traffic Permutations for Mesh On-Chip Networks
%J Optimization and On-chip Communication
%@ 0975-8887
%V OOC
%N 1
%P 6-10
%D 2012
%I International Journal of Computer Applications
Abstract

Networks-on-Chip (NoC) is recently proposed as an alternative to the on-chip bus to meet the increasing requirement of complex communication needs in Systems-on-Chip (SoC). Using on-chip interconnection networks in place of ad-hoc global wiring, structures the top level wires on a chip and facilitates modular design. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. Using a network to replace global wiring has advantages of structure, performance, and modularity. With this approach, system modules (processors, memories, peripherals, etc.) communicate by sending packets to one another over the network. In NoC, nodes are arranged in the topology such that communication between any nodes is possible even though they are not directly connected. Each node is a IP core which can be a DSP, Microprocessor, Memory along with routing function which is responsible for forwarding the data packet to the neighboring node.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Network on Chip XY routing Traffic Patterns Interconnection Networks Simulation