|Recent Trends in Engineering Technology
|Foundation of Computer Science USA
|RETRET - Number 1
|Authors: Ashish S. Shende, M. A. Gaikwad, D. R. Dandekar
Ashish S. Shende, M. A. Gaikwad, D. R. Dandekar . Application of Current-Mode Multi-Valued Logic in the Design of Vedic Multiplier. Recent Trends in Engineering Technology. RETRET, 1 (March 2013), 13-16.
Vedic multiplier is based on ancient Indian Vedic mathematics that offers simpler and hierarchical structure. Multi-valued logic results in the effective utilization of interconnections, which reduces the chip size and delay. This paper proposes that if the potential of multi-valued logic is combined with simplicity of Vedic architecture, it may result in an efficient multiplier design. Since the performance of a digital signal processor depends mainly on the multipliers used, the proposed approach can greatly enhance the performance of a digital signal processor.