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Review of XY Routing Algorithm for 2D Torus Topology of NoC Architecture

IJCA Special Issue on Recent Trends in Engineering Technology
© 2013 by IJCA Journal
Year of Publication: 2013
Priyanka N. Chopkar
Mahendra A. Gaikwad

Priyanka N Chopkar and Mahendra A Gaikwad. Article: Review of XY Routing Algorithm for 2D Torus Topology of NoC Architecture. IJCA Special Issue on Recent Trends in Engineering Technology RETRET:22-26, March 2013. Full text available. BibTeX

	author = {Priyanka N. Chopkar and Mahendra A. Gaikwad},
	title = {Article: Review of XY Routing Algorithm for 2D Torus Topology of NoC Architecture},
	journal = {IJCA Special Issue on Recent Trends in Engineering Technology},
	year = {2013},
	volume = {RETRET},
	pages = {22-26},
	month = {March},
	note = {Full text available}


Network on Chip (NoC) is an approach to designing the communication subsystem between IP cores in a System on a Chip (SoC). NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs. The purpose of NOC is to solve the choke point in communication and the clock problem from architecture. Each route in NOC includes some routers, and it takes a few clock periods by passing a router. When the network is in congestion, the package transmission will produce much more time delay. So adopting a appropriate routing algorithm to get the balance between the time delay and throughput rate becomes the key problem. This paper basically review of XY routing algorithm for 2D torus topology of Network on chip architecture for constant bit rate (CBR) random traffic in NIRGAM simulator to reduce the average latency per packet and increase average throughput.


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