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Reseach Article

Review of XY Routing Algorithm for 2D Torus Topology of NoC Architecture

Published on March 2013 by Priyanka N. Chopkar, Mahendra A. Gaikwad
Recent Trends in Engineering Technology
Foundation of Computer Science USA
RETRET - Number 1
March 2013
Authors: Priyanka N. Chopkar, Mahendra A. Gaikwad

Priyanka N. Chopkar, Mahendra A. Gaikwad . Review of XY Routing Algorithm for 2D Torus Topology of NoC Architecture. Recent Trends in Engineering Technology. RETRET, 1 (March 2013), 22-26.

author = { Priyanka N. Chopkar, Mahendra A. Gaikwad },
title = { Review of XY Routing Algorithm for 2D Torus Topology of NoC Architecture },
journal = { Recent Trends in Engineering Technology },
issue_date = { March 2013 },
volume = { RETRET },
number = { 1 },
month = { March },
year = { 2013 },
issn = 0975-8887,
pages = { 22-26 },
numpages = 5,
url = { /specialissues/retret/number1/10882-1310/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Special Issue Article
%1 Recent Trends in Engineering Technology
%A Priyanka N. Chopkar
%A Mahendra A. Gaikwad
%T Review of XY Routing Algorithm for 2D Torus Topology of NoC Architecture
%J Recent Trends in Engineering Technology
%@ 0975-8887
%N 1
%P 22-26
%D 2013
%I International Journal of Computer Applications

Network on Chip (NoC) is an approach to designing the communication subsystem between IP cores in a System on a Chip (SoC). NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs. The purpose of NOC is to solve the choke point in communication and the clock problem from architecture. Each route in NOC includes some routers, and it takes a few clock periods by passing a router. When the network is in congestion, the package transmission will produce much more time delay. So adopting a appropriate routing algorithm to get the balance between the time delay and throughput rate becomes the key problem. This paper basically review of XY routing algorithm for 2D torus topology of Network on chip architecture for constant bit rate (CBR) random traffic in NIRGAM simulator to reduce the average latency per packet and increase average throughput.

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Index Terms

Computer Science
Information Sciences


Network On Chip (noc) 2d Torus Topology Xy Routing Algorithm