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Reseach Article

A Comparative Study of Different Topologies for Network-On-Chip Architecture

Published on March 2013 by Sonal S. Bhople, M. A. Gaikwad
Recent Trends in Engineering Technology
Foundation of Computer Science USA
RETRET - Number 1
March 2013
Authors: Sonal S. Bhople, M. A. Gaikwad
cddfd171-6fd1-4133-9e07-905b2b1378d4

Sonal S. Bhople, M. A. Gaikwad . A Comparative Study of Different Topologies for Network-On-Chip Architecture. Recent Trends in Engineering Technology. RETRET, 1 (March 2013), 27-29.

@article{
author = { Sonal S. Bhople, M. A. Gaikwad },
title = { A Comparative Study of Different Topologies for Network-On-Chip Architecture },
journal = { Recent Trends in Engineering Technology },
issue_date = { March 2013 },
volume = { RETRET },
number = { 1 },
month = { March },
year = { 2013 },
issn = 0975-8887,
pages = { 27-29 },
numpages = 3,
url = { /specialissues/retret/number1/10883-1312/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 Recent Trends in Engineering Technology
%A Sonal S. Bhople
%A M. A. Gaikwad
%T A Comparative Study of Different Topologies for Network-On-Chip Architecture
%J Recent Trends in Engineering Technology
%@ 0975-8887
%V RETRET
%N 1
%P 27-29
%D 2013
%I International Journal of Computer Applications
Abstract

Network on Chip (NoC) is one solution for designing communication among components in the SoC circuits with several billion transistors that will reach the market in approximately 5-10 years from now. Different topologies having various advantages according to their applications. This paper present brief idea about topologies depending on parameter.

References
  1. A Delay-Aware Topology-based Design for Network-on-chip Applications By Haytham Elmiligi, Ahmed A. Morgan, M. Watheq El-Kharashi, Fayez Gebali. IEEE transaction, 2009.
  2. M. Mirza-Aghatabar+,S. Koohi+, S. Hessabi*, M. Pedram†," An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models", IEEE International Conference on Digital System DSD 2007.
  3. L. Benini and D. Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, 35 p. 70 (2002).
  4. B. H. Meyer, J. J. Pieper, J. M. Paul, J. E. Nelson, S. M. Pieper and A. G. Rowe, "Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors," IEEE transactions on Computers, vol. 54, no. 6, pp. 684-697, Jun 2005.
  5. M. Palesi, R. Holsmark, S. Kumar, and V. Catania, " Application specific routing algorithms for network on chip," IEEE Transactions on Parallel and Distributed Systems, vol. 20, no3 pp. 316-339,2009.
  6. Khalid Latif, Tiberiu Seceleanu, Hannu Tenhunen, Power and Area Efficient Design of Network-on-Chip Router Through Utilization of Idle Buffers.
  7. M. Nickray, M. Dehyadgari, and A. Afzali-kusha, "Power and Delay optimization for network on chip," in Proceedings of the 2005 European Conference on Circuit Theory and Designs, Cork, Ireland, Aug-28-2 Sept. 2005, pp. 273-276.
  8. T. Bjerregaard and K. Mahadevan, " A survey of research and practices of network-on-chip,"ACM Computing Surveys, vol. 38, pp. 38, pp. 1-51, Mar. 2006.
  9. A. Chien, " A cost and speed model for k-ary n-Cube Wormhole Routers," IEEE transactions on Parallel and Distributed Systems, vol. 9, no2, pp 29-36, Feb 1998.
  10. Cheng Liu•, Liyi Xiao, Fangfa Fu, Design and Analysis of On-Chip Router.
  11. L. S. Peh and W. J. Dalley, A delay model for router michroarchitectures," IEEE Micro, vol. 21, no. 1, pp. 26-34, Jan. 2001.
  12. W. Zhou, Y. Zhang, and Z. Mao," An application specific NOC mapping for optimized delay," in proceeding of the IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology ,Tunis, Tunisia , Sept. 5-7, 2006, pp. 184-188.
  13. V. Pavlidis and E. Friedman," Interconnect-based design methodologies for three-dimensional integrated circuits'' Proceeding of the IEEE, vol. 97, no. 1, pp 123-140, 2009.
  14. V. Dumitriu and G. N. Khan, "Throughput- oriented NOC topology generation and analysis for high performance SOC ," IEEE Transactions on VLSI Systems, vol. in press 2009.
  15. H. Elmiligi, A. A. Morgan, M. W. EI-Kharashi and F. Gebli, " A reliability-aware design methodology for network-on-chip applications," in proceeding of the IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology ,Era Cario, Egypt, Apr. 6-9, 2009, pp. 107-112.
  16. H. Elmiligi, A. Morgan, M. W. EI-Kharashi and F. Gebli, " Power Aware Topology Optimization for Network-on-chips," in proceeding of the IEEE International Symposium on Circuits and SystemsConference on Design and Test of Integrated Systems in Nanoscale Technology ,Era Cario, Egypt, Apr. 6-9, 2009, pp. 107-112.
  17. Victor Dumitriu and Gul N. Khan, "Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs", IEEE transactions on very large scale integration (vlsi) systems, vol. 17, no. 10, october 2009.
  18. Mahmoud Moadeli1, Ali Shahrabi2, Wim Vanderbauwhede1, Mohamed Ould-Khaoua1," An Analytical Performance Model for the Spidergon NoC",IEEE 21st International Conference on Advanced Networking and Applications(AINA'07) 2007.
Index Terms

Computer Science
Information Sciences

Keywords

System On Chip Network On Chip Different Topologies And Topology Parameter