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Test Access Port and Scan Based Technique of In-System Timing Extraction and Control

by Richa Maheshwari, Neeta Awasthi
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 1 - Number 17
Year of Publication: 2010
Authors: Richa Maheshwari, Neeta Awasthi
10.5120/368-555

Richa Maheshwari, Neeta Awasthi . Test Access Port and Scan Based Technique of In-System Timing Extraction and Control. International Journal of Computer Applications. 1, 17 ( February 2010), 21-24. DOI=10.5120/368-555

@article{ 10.5120/368-555,
author = { Richa Maheshwari, Neeta Awasthi },
title = { Test Access Port and Scan Based Technique of In-System Timing Extraction and Control },
journal = { International Journal of Computer Applications },
issue_date = { February 2010 },
volume = { 1 },
number = { 17 },
month = { February },
year = { 2010 },
issn = { 0975-8887 },
pages = { 21-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume1/number17/368-555/ },
doi = { 10.5120/368-555 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T19:43:07.273005+05:30
%A Richa Maheshwari
%A Neeta Awasthi
%T Test Access Port and Scan Based Technique of In-System Timing Extraction and Control
%J International Journal of Computer Applications
%@ 0975-8887
%V 1
%N 17
%P 21-24
%D 2010
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Historically, most Printed Circuit Board (PCB) testing was done using bed-of-nail in-circuit test equipment. The progress in the field of miniaturization and integration density has possible to design very complex PCBs, which presents very high testability requirements. Boundary scan is now the most promising technology for testing high complexity PCBs. This paper presents scan-based test access port standard for testing complex ICs and also presents a method which allow the extraction of fine-grained timing information using Test Access Port (TAP).

References
  1. IEEE Standards Committee. IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE, 345 East 47th Street, New York, NY 10017-2394, July 1990. IEEE Std 1149.1-1990.
  2. Andr´e DeHon, Thomas F. Knight Jr., and Thomas Simon. Automatic Impedance Control. In ISSCC Digest of Technical Papers, pages 164-165. IEEE, February 1993.
  3. Mark Horowitz, Andy Chan, Joe Cobrunson, Jim Gasbarro, Thomas Lee, Wing Leung, Wayne Richardson, Tim Thrush, and Yasuhiro Fujii. PLL Design for a 500MB/s Interface. In ISSCC Digest of Technical Papers, pages 160-161. IEEE, February 1993.
  4. Mark G. Johnson. A Variable Delay Line PLL for CPU-Coprocessor Synchronization. IEEE Journal of Solid-State Circuits, 23(5):1218-1223, October 1988.
Index Terms

Computer Science
Information Sciences

Keywords

Printed Circuit Board (PCB) Test Access Port (TAP)

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