The week's pick
Random Articles
Reseach Article
NANO Scale SOI MOSFET Structures and Study of Performance Factors
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 1 - Number 28 |
| Year of Publication: 2010 |
| Authors: Prakash Baviskar, Prasad Vinchurkar, Sanjeev Jain |
10.5120/513-830
|
Prakash Baviskar, Prasad Vinchurkar, Sanjeev Jain . NANO Scale SOI MOSFET Structures and Study of Performance Factors. International Journal of Computer Applications. 1, 28 ( February 2010), 36-41. DOI=10.5120/513-830
Abstract
This paper proposes a study related with the downscaling trend in CMOS devices. Some of the structural variants of the MOSFET have been explored and the key performance factors as gate tunneling current, transconductance and output conductance are discussed. The impact of energy quantization on gate tunneling current is studied for double-gate and ultra thin body MOSFETS. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage. Very high transconductance, approaching the ballistic limit, can be achieved provided that technological improvements further increase the electron mobility in the silicon film. The output conductance and Early voltage are severely affected by length scaling as channel length-modulation (CLM) and drain-induced barrier lowering (DIBL) effects become more important, but they are acceptable for channel lengths above 15 nm.
References
- Wei Ma , “Linearity Analysis of Single and Double-Gate SOI MOSFET Transistor” thesis submitted Aug. 2004.
- Zhibin Ren , “Nanoscale MOSFETS”: Physics, Simulation and Design, Thesis Submitted to the Faculty of Purdue University.
- Hon-sum Philip Wong, , David J. frank, “Nanoscale CMOS, proceedings of the IEEE, vol. 87, no. 4, April 1999,
- D. Fried, et. al, “A Fin-type independent- double-gate NFET”,Device Research Conference, 2003
- L. Mathew, et. al, “CMOS vertical multiple independent gate field effect transistors (MIGFET)”, Int. SOI Conf., 2004.
- S. Mukhopadhyay, et. al, “Modeling and Analysis of Total Leakage Currents in Nanoscale Double Gate Devices and Circuits”, presented in ISLPED, 2005
- K. Kim, et. al, “Nanoscale CMOS circuit Leakage power reduction by Double-Gate devices”, ISLPED, 2004.
- Leland Chang, Kevin J. Yang, Yee-Chia Yeo, “Direct-Tunneling Gate Leakage Current in Double-Gate and Ultrathin Body MOSFETs” IEEE Transactions on electron devices, vol. 49, no. 12, December 2002.
- D. Jiménez, B. Iñíguez, “Analog performance of the nanoscale double-gate metal-oxide- semiconductor field-effect-transistor near the ultimate scaling limits”, Journal Of Applied Physics Volume 96, Number 9 1 November 2004.
- Thomas Ernst, Sorin Cristoloveanu, Gérard Ghibaudo, “Ultimately Thin Double-Gate SOI MOSFETs”,IEEE Transactions on electron devices, vol. 50, no. 3, march 2003.
- Yajun An, “Device Modeling Study of Vertical Channel SiGe MOSFETs” A thesis submitted at UNIVERSITY OF CINCINNATI.
- V. Kilchytska, T.M. Chung, J.-P. Raskin, D. Flandre, “Investigation of Charge Control Related Performances In Double-Gate SOI MOSFETs”.
Index Terms
Keywords