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Performance Improvement in Large Graph Algorithms on GPU using CUDA: an Overview

International Journal of Computer Applications
© 2010 by IJCA Journal
Number 10 - Article 4
Year of Publication: 2010
Swapnil D. Joshi
Mrs. V. S. Inamdar

Swapnil D Joshi and Mrs. V S Inamdar. Article:Performance Improvement in Large Graph Algorithms on GPU using CUDA: An Overview. International Journal of Computer Applications 10(10):10–14, November 2010. Published By Foundation of Computer Science. BibTeX

	author = {Swapnil D. Joshi and Mrs. V. S. Inamdar},
	title = {Article:Performance Improvement in Large Graph Algorithms on GPU using CUDA: An Overview},
	journal = {International Journal of Computer Applications},
	year = {2010},
	volume = {10},
	number = {10},
	pages = {10--14},
	month = {November},
	note = {Published By Foundation of Computer Science}


The basic operations on the graphs with millions of vertices are common in various applications. To have faster execution of such operations is very essential to reduce overall computation time. Today’s Graphics processing units (GPUs) have high computation power and low price. This device can be treated as an array of Single Instruction Multiple Data (SIMD) processors using CUDA software interface by Nvidia. Massively Multithreaded architecture of a CUDA device makes various threads to run in parallel and hence making optimum use of available computation power of GPU. In case of graph algorithms, vertices of the graphs are processed in parallel by mapping them to various threads on device. By making thousands of threads to run in parallel, computation time required for these algorithms is drastically decreased as compared to their CPU implementation.

We studied different parallel algorithms for Breadth first search, all pairs shortest path that are carried out on GPU using CUDA and make their comparative study with respect to execution time, data structure used, input data etc. In the paper, we presented overview of various parallel methods carried out on GPU using its multithreaded architecture for BFS, APSP by various authors.


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