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Reseach Article

Low Power ALU Design considering PVT Variations

by D. Anitha, K. Manjunatha Chari, P. Satish Kumar
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 104 - Number 17
Year of Publication: 2014
Authors: D. Anitha, K. Manjunatha Chari, P. Satish Kumar
10.5120/18300-9442

D. Anitha, K. Manjunatha Chari, P. Satish Kumar . Low Power ALU Design considering PVT Variations. International Journal of Computer Applications. 104, 17 ( October 2014), 19-23. DOI=10.5120/18300-9442

@article{ 10.5120/18300-9442,
author = { D. Anitha, K. Manjunatha Chari, P. Satish Kumar },
title = { Low Power ALU Design considering PVT Variations },
journal = { International Journal of Computer Applications },
issue_date = { October 2014 },
volume = { 104 },
number = { 17 },
month = { October },
year = { 2014 },
issn = { 0975-8887 },
pages = { 19-23 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume104/number17/18300-9442/ },
doi = { 10.5120/18300-9442 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:36:25.373024+05:30
%A D. Anitha
%A K. Manjunatha Chari
%A P. Satish Kumar
%T Low Power ALU Design considering PVT Variations
%J International Journal of Computer Applications
%@ 0975-8887
%V 104
%N 17
%P 19-23
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

ALU is one of the most important components in a microprocessor that carries out the arithmetic and logical operations. This paper highlights the techniques in designing a low power ALU in nanometer CMOS. Different 10 transistor full adders are compared and chosen the Full adder with least power dissipation to obtain low power and area efficient ALU. The power is reduced by 78% when compared to the existing ALU which is designed using XOR based Full adder. The proposed design does not compromise with the performance as the full adder delay is less. The functionality of the design remains the same despite the temperature and voltage variations. The power dissipation for different temperatures ranging from -50 0C to +50 0C has been observed. The ultimate goal is to design an ALU with the least number of transistors thereby decreasing the area and power consumption in the overall circuit that takes shape at the end.

References
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Index Terms

Computer Science
Information Sciences

Keywords

ALU CMOS power dissipation full adder