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RSA Cryptography using our Designed Processor and MicroBlaze Soft Processor in FPGAs

by Md. Nazrul Islam Mondal, Md. Al Mamun, Boshir Ahmed
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 104 - Number 8
Year of Publication: 2014
Authors: Md. Nazrul Islam Mondal, Md. Al Mamun, Boshir Ahmed
10.5120/18224-9366

Md. Nazrul Islam Mondal, Md. Al Mamun, Boshir Ahmed . RSA Cryptography using our Designed Processor and MicroBlaze Soft Processor in FPGAs. International Journal of Computer Applications. 104, 8 ( October 2014), 25-31. DOI=10.5120/18224-9366

@article{ 10.5120/18224-9366,
author = { Md. Nazrul Islam Mondal, Md. Al Mamun, Boshir Ahmed },
title = { RSA Cryptography using our Designed Processor and MicroBlaze Soft Processor in FPGAs },
journal = { International Journal of Computer Applications },
issue_date = { October 2014 },
volume = { 104 },
number = { 8 },
month = { October },
year = { 2014 },
issn = { 0975-8887 },
pages = { 25-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume104/number8/18224-9366/ },
doi = { 10.5120/18224-9366 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:35:38.560067+05:30
%A Md. Nazrul Islam Mondal
%A Md. Al Mamun
%A Boshir Ahmed
%T RSA Cryptography using our Designed Processor and MicroBlaze Soft Processor in FPGAs
%J International Journal of Computer Applications
%@ 0975-8887
%V 104
%N 8
%P 25-31
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Some applications such as RSA encryption/decryption need integer arithmetic operations with many bits. However, such operations cannot be performed directly by conventional CPUs, because their instruction supports integers with fixed bits, say, 64 bits. Since the CPUs need to repeat arithmetic operations to numbers with fixed bits, they have considerably overhead to execute applications involving integer arithmetic with many bits. On the other hand, This paper implements hardware algorithms for such applications in the FPGAs for further acceleration. However, the implementation of hardware algorithm is usually very complicated and debugging of hardware is too hard. The main contribution of this paper is to present an intermediate approach of software and hardware using FPGAs. More specifically, this paper presents a processor based on FDFM (Few DSP slices and Few Memory blocks) approach that supports arithmetic operations with flexibly many bits, and implement it in the FPGA. To show the potentiality of designed processor, 128-bit RSA encryption/decryption is implemented and compare with soft processor "MicroBlaze" in FPGA. The resulting processor uses only one DSP48E1 slice and four Block RAMs (BRAMs), and RSA encryption software on it runs in 0. 42ms. However, MicroBlaze uses three DSP48E1 slices and 170 Block RAMs (BRAMs) and runs in 152. 28ms. Hence, the proposed designed processor is significantly efficient in terms of resource used and time complexity in comparison to soft processor "MicroBlaze" in FPGAs. Also the proposed processor can be used efficiently for longer bit arithmetic operation such as 2048-bit without further modifications and hence it is more flexible.

References
  1. VIRTEX-6 FPGA Memory Resources (V1. 5), Xilinx Inc. , 2010.
  2. VIRTEX 6 ML605 Hardware USER GUIDE (V1. 2. 1), Xilinx Inc. , 2010.
  3. VIRTEX-6 FPGA DSP48E1 SLICE USER GUIDE (V1. 3), Xilinx Inc. , 2011.
  4. J. Bordim, Y. Ito, and K. Nakano, "Accelerating the CKY parsing using FPGAs," IEICE Transactions on Information and Systems, vol. E86-D, no. 5, pp. 803–810, 2003.
  5. J. L. Bordim, Y. Ito, and K. Nakano, "Instance-specific solutions to accelerate the CKY parsing for large context-free grammars," International Journal on Foundations of Computer Science, vol. 15, no. 2, pp. 403–416, 2004.
  6. Y. Ito and K. Nakano, "A hardware-software cooperative approach for the exhaustive verification of the Collatz conjecture," in Proc. of International Symposium on Parallel and Distributed Processing with Applications, 2009, pp. 63–70.
  7. K. Nakano and Y. Yamagishi, "Hardware n choose k counters with applications to the partial exhaustive search," IEICE Transactions on Information and Systems, vol. E88-D, no. 7, 2005.
  8. Y. Ito and K. Nakano, "Efficient exhaustive verification of the Collatz conjecture using DSP blocks of Xilinx FPGAs," International Journal of Networking and Computing, vol. 1, no. 1, pp. 19–62, 2011.
  9. K. Nakano and E. Takamichi, "An image retrieval system using FPGAs," IEICE Transactions on Information and Systems, vol. E86-D, no. 5, pp. 811–818, May 2003.
  10. Y. Ago, Y. Ito, and K. Nakano, "An FPGA implementation for neural networks with the FDFM processor core approach," International Journal of Parallel, Emergent and Distributed Systems, vol. 28, no. 4, pp. 308–320, 2013.
  11. Y. Ito and K. Nakano, "Low-latency connected component labeling using an FPGA," International Journal of Foundations of Computer Science, vol. 21, no. 03, pp. 405–425, 2010.
  12. X. Zhou, N. Tomagou, Y. Ito, and K. Nakano, "Efficient Hough transform on the FPGA using DSP slices and block RAMs," in Proc. of International Parallel and Distributed Processing Symposium Work-shops, May 2013, pp. 771–778.
  13. VIRTEX-6 FPGA DSP48E1 SLICE USER GUIDE (V1. 2), Xilinx Inc. , 2009.
  14. Y. Ago, A. Inoue, K. Nakano, and Y. Ito, "The parallel FDFM processor core approach for neural networks," in Proc. of International Conference on Networking and Computing, December 2011, pp. 113–119.
  15. S. Bo, K. Kawakami, K. Nakano, and Y. Ito, "An RSA encryption hardware algorithm using a single DSP Block and single Block RAM on the FPGA," International Journal of Networking and Computing, vol. 1, no. 2, pp. 277–289, July 2011.
  16. Y. Ito, K. Nakano, and S. Bo, "The parallel FDFM processor core approach for CRT-based RSA decryption," International Journal of Networking and Computing, vol. 2, pp. 56–78, 2012.
  17. K. Nakano, K. Kawakami, and K. Shigemoto, "RSA encryption and decryption using the redundant number system on the FPGA," in In Proc. IEEE International Symposium on Parallel and Distributed Processing, May 2009, pp. 1–8.
  18. R. L. Rivest, A. Shamir, and L. Adleman, "A method for obtaining digital signatures and public-key cryptosystems," Commun. ACM, vol. 21, no. 2, pp. 120-126, 1978
  19. T. Blum and C. Paar, "Montgomery modular exponentiation on recon-figurable hardware," in Proc. of the 14th IEEE Symposium on Computer Arithmetic, 1999, pp. 70–77.
  20. P. L. Montgomery, "Modular multiplication without trial division," Math. of Comput. , vol. 44, pp. 519–521, 1985.
  21. A. F. Tenca and C. K. Koc¸, "A scalable architecture for Montgomery multiplication," in Proc. of the First International Workshop on Crypto-graphic Hardware and Embedded Systems, 1999, pp. 94–108.
  22. M. Niimura and Y. Fuwa, "Improvement of radix-2k signed-digit number for high speed circuit," Formalized Mathematics, vol. 11, no. 2, 133–137, January 2003
  23. Md. Nazrul Islam Mondal, Kohan Sai, K. Nakano, and Y. Ito, "A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs," In Proc. of the First International Symposium on Computing and Networking (CANDAR'13), pp. 75–84, December 2013.
Index Terms

Computer Science
Information Sciences

Keywords

Multiple-Length-Arithmetic MicroBlaze Soft Processor Montgomery Modular Multiplication in RSA FPGA DSP Slices Block RAMs.

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