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Reseach Article

Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis

by Md. Riazur Rahman
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 108 - Number 2
Year of Publication: 2014
Authors: Md. Riazur Rahman

Md. Riazur Rahman . Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis. International Journal of Computer Applications. 108, 2 ( December 2014), 7-12. DOI=10.5120/18881-0160

@article{ 10.5120/18881-0160,
author = { Md. Riazur Rahman },
title = { Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis },
journal = { International Journal of Computer Applications },
issue_date = { December 2014 },
volume = { 108 },
number = { 2 },
month = { December },
year = { 2014 },
issn = { 0975-8887 },
pages = { 7-12 },
numpages = {9},
url = { },
doi = { 10.5120/18881-0160 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T22:41:55.830853+05:30
%A Md. Riazur Rahman
%T Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis
%J International Journal of Computer Applications
%@ 0975-8887
%V 108
%N 2
%P 7-12
%D 2014
%I Foundation of Computer Science (FCS), NY, USA

Fault Tolerant reversible decoders are the prerequisite of high performance computing systems. In this paper, an optimized reversible fault tolerant decoder has been proposed by using novel cost effective gates named Reversible Fault Tolerant Decoder (RDC) and Double Fredkin Gate (DFG). Several lower bounds on the numbers of gates, garbage and quantum costs are also proposed to generalize the architecture of n-to-2n reversible decoder. The comparative performance analysis shows that the proposed design outperforms the existing designs in terms of number of gates used, quantum cost, delay, ancilla inputs and design complexity.

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Index Terms

Computer Science
Information Sciences


Reversible Decoder Circuit Quantum Computing Fault Tolerant Low Power Computing.