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Article:Implementation of Low Power Scalable Encryption Algorithm

by K.J. Jegadish Kumar, S. Salivahanan, K. Chenna Kesava Reddy
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 11 - Number 1
Year of Publication: 2010
Authors: K.J. Jegadish Kumar, S. Salivahanan, K. Chenna Kesava Reddy
10.5120/1548-2060

K.J. Jegadish Kumar, S. Salivahanan, K. Chenna Kesava Reddy . Article:Implementation of Low Power Scalable Encryption Algorithm. International Journal of Computer Applications. 11, 1 ( December 2010), 14-18. DOI=10.5120/1548-2060

@article{ 10.5120/1548-2060,
author = { K.J. Jegadish Kumar, S. Salivahanan, K. Chenna Kesava Reddy },
title = { Article:Implementation of Low Power Scalable Encryption Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { December 2010 },
volume = { 11 },
number = { 1 },
month = { December },
year = { 2010 },
issn = { 0975-8887 },
pages = { 14-18 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume11/number1/1548-2060/ },
doi = { 10.5120/1548-2060 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T19:59:28.476233+05:30
%A K.J. Jegadish Kumar
%A S. Salivahanan
%A K. Chenna Kesava Reddy
%T Article:Implementation of Low Power Scalable Encryption Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 11
%N 1
%P 14-18
%D 2010
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Scalable Encryption algorithm (SEA) is a symmetric block cipher, especially designed for resources constrain systems. SEA proposes low cost encryption routines (i.e. small code size, memory and power), targeted for processors with a limited instruction set. SEA is parametric with text, key and processor size, and allows efficient combination of encryption/decryption and key derivation. SEA was initially designed for software implementations in controllers, smart cards, or processors and small embedded applications. In this paper, we investigate the performance of SEA in a Field programmable gate array (FPGA) device. For this purpose, an iterative loop design of the block cipher is implemented on FPGA. Beyond its low cost performances, the proposed architecture is fully flexible with any parameters and takes advantage of generic VHDL coding. Our efficient modular adders implementation achieves lower area, power consumption and considerably higher throughputs on the target platform VIRTEX-4, xc4vl25 and SPARTAN-3, xc3s1400.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Block ciphers constrained applications FPGA implementation