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Launch and Capture Power Reduction using Data Encoding and Precomputation Technique

by R.deepika, V.sinduja
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 112 - Number 11
Year of Publication: 2015
Authors: R.deepika, V.sinduja
10.5120/19713-1483

R.deepika, V.sinduja . Launch and Capture Power Reduction using Data Encoding and Precomputation Technique. International Journal of Computer Applications. 112, 11 ( February 2015), 28-31. DOI=10.5120/19713-1483

@article{ 10.5120/19713-1483,
author = { R.deepika, V.sinduja },
title = { Launch and Capture Power Reduction using Data Encoding and Precomputation Technique },
journal = { International Journal of Computer Applications },
issue_date = { February 2015 },
volume = { 112 },
number = { 11 },
month = { February },
year = { 2015 },
issn = { 0975-8887 },
pages = { 28-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume112/number11/19713-1483/ },
doi = { 10.5120/19713-1483 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:49:14.391218+05:30
%A R.deepika
%A V.sinduja
%T Launch and Capture Power Reduction using Data Encoding and Precomputation Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 112
%N 11
%P 28-31
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Testing of VLSI circuits aims for high quality screening of circuits by targeting performance related faults. The main objective of testing is to generate compact test set which is used to detect multiple faults present in the circuit, which results in increase of switching activity hence the pattern should be optimized without losses in performance of the circuit. Design for Testability mechanism is used for launch-off shift and launch-off capture testing and it supports design partitioning approach in which one region is tested at a time results in launch and capture power reduction in a design flow compatible manner. Data encoding scheme is used to reduce the power dissipation by the means of reducing the switching activity which involves comparison of two bits at a time. By using precomputation technique which involves comparison of single bit at a time starting from its MSB to LSB, the power dissipation is reduced up to 20% compared to data encoding technique.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Design partitioning Launch-off capture (LOC) Launch-off shift (LOS) Peak power reduction Test power reduction.

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