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Reseach Article

FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase

by Abhay Sharma
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 116 - Number 17
Year of Publication: 2015
Authors: Abhay Sharma
10.5120/20430-2760

Abhay Sharma . FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase. International Journal of Computer Applications. 116, 17 ( April 2015), 27-31. DOI=10.5120/20430-2760

@article{ 10.5120/20430-2760,
author = { Abhay Sharma },
title = { FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase },
journal = { International Journal of Computer Applications },
issue_date = { April 2015 },
volume = { 116 },
number = { 17 },
month = { April },
year = { 2015 },
issn = { 0975-8887 },
pages = { 27-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume116/number17/20430-2760/ },
doi = { 10.5120/20430-2760 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:57:24.737006+05:30
%A Abhay Sharma
%T FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase
%J International Journal of Computer Applications
%@ 0975-8887
%V 116
%N 17
%P 27-31
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Tree Multipliers are frequently used to reduce the delay of array multipliers. The objective of tree multipliers is to utilize the concept of carry save adders in reducing the partial product. Two well known tree multipliers Wallace and Dadda uses full adders and half adders for the aforesaid purpose. This paper implements a multiplier which will perform reduction of partial products using 4 bit Carry Lookahead Adders primarily instead of Full adders. This will result in fewer reduction stages as Full adders reduces 3 partial products bits to 2 giving a 1. 5 to 1 ratio whereas 4 bit CLA will reduce 9 partial products bits to 5 giving 1. 8 to 1 ratio. Xilinx Spartan 3E FPGA board is used for implementation of structural verilog code for the multiplier design.

References
  1. C. S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Transactions on Electronic Computers, vol. 13, pp. 14-17, 1964.
  2. L. dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349-356, 1965.
  3. Behrooz Prahami, Computer Arithmetic Algorithms and Hardware Designs, New York: Oxford University Press, 1999.
  4. Pong P. Chu, FPGA Prototyping by Verilog examples: Xilinx Spartan 3 Version, John Wiley & Sons Publication, 2008.
  5. M. Morris Mano, Ciletti, Digital Design, 4th edition, Pearson, 2008.
  6. W. Chu, A. I. Unwala, P. Wu & E. E. Swartzlander, Jr. , "Implementation of a High Speed Multiplier Using Carry Lookahead Adders," Asilomar, pp. 400-404, 2013.
  7. Samir Palnitkar, "Verilog HDL: A Guide to Digital Design and Synthesis," 2nd Edition, Pearson, 2003.
  8. Shruti Dixit, Praveen Kumar Pandey, "FPGA implementation of Wallace tree multiplier using CSLA/CLA," International Journal of Science and Research, vol. 2, issue 12, pp. 314-318, Dec. 2013.
Index Terms

Computer Science
Information Sciences

Keywords

FPGA Multiplier Wallace Dadda Carry Lookahead Adders.