The week's pick
Reseach Article
Cost Efficient Design of Reversible Adder Circuits for Low Power Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 117 - Number 19 |
| Year of Publication: 2015 |
| Authors: Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya, Amit Kumar |
10.5120/20665-3408
|
Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya, Amit Kumar . Cost Efficient Design of Reversible Adder Circuits for Low Power Applications. International Journal of Computer Applications. 117, 19 ( May 2015), 37-45. DOI=10.5120/20665-3408
Abstract
A large amount of research is currently going on in the field of reversible logic, which have low heat dissipation, low power consumption, which is the main factor to apply reversible in digital VLSI circuit design. This paper introduces reversible gate named as 'Inventive0 gate'. The novel gate is synthesis the efficient adder modules with minimum garbage output and gate count. The Inventive0 gate capable of implementing a 4-bit ripple carry adder and carry skip adders. It is presented that Inventive0 gate is much more efficient and optimized approach as compared to their existing design, in terms of gate count, garbage outputs and constant inputs. In addition, some popular available reversible gates are implemented in the MOS transistor design the implementation kept in mind for minimum MOS transistor count and are completely reversible in behaviour more precise forward and backward computation. Lesser architectural complexity show that the novel designs are compact, fast as well as low power.
References
- C. H. Bennett. 1973. Logical reversibility of Computation, IBM Journal Research and Development. 17, 525-532.
- R. Landauer. 1961. Irreversibility and Heat Generation in the Computing Process. IBM Journal of Research and Development, 5(3), 183-191.
- Diganta Sengupta, Mahamuda Sultana, Atal Chaudhuri. 2011. Relization of a Novel Reversible SCG Gate and its Application for designing Parallel adder/subtractor and match logic. International Journal of Computer Applications, v 31(9), 30-34.
- Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh. 2014. An Inventive Design of 4*4 Bit Reversible NS Gate. IEEE International Conference on Recent Advances and Innovation in Engineering (ICRAIE-2014), 1-6.
- Himanshu Thapliyal and Nagarajan Ranganathan. 2011. A New reversible design of BCD adder. In proceeding of the design Automation and test in Europe (DATE). Grenoble. France. 1180-1183.
- Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh. 2014. Preternatural Low-Power Reversible Decoder Design in 90 nm Technology Node. International Journal of Scientific & Engineering Research. 5(6). 969-978.
- Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari. 2012. Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design, Hindawi Publishing Corporation VLSI Design.
- Michael P. Frank. 2005. Introduction to Reversible Computing: Motivation, Progress, and Challenges, Proceedings of the 2nd conference on computing frontier Ischia, Italy, 385-390.
- Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh, 2014. Evolution of structure of some binary group-based n-bit comparator, n-to-2n decoder by reversible technique, International Journal of VLSI design & Communication Systems (VLSICS), v 5(5), 9-22
- Neeraj Kumar Misra, Subodh Wairya and Vinod Kumar Singh. 2015. Approaches to Design Feasible Error Control Scheme Based on Reversible Series Gates. European Journal of Scientific Research. vol. 129, no. 3, 224-240.
- Md. M. H Azad Khan, 2002. Design of Full-adder With Reversible Gates. International Conference on Computer and Information Technology, Dhaka, Bangladesh, 515-519.
- Neeraj Kumar Mishra et al. , 2013. An advancement in the NxN Multiplier Architecture Realization via the Ancient indian Vedic Mathematics, International Journal of Electronics Communication and Computer Engineering, vol (4), Issue(2), 2278-4209.
- Bibhash Sen, et al,. 2013. Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA, ISRN Electronics Hindawi Publishing Corporation.
- Hafiz Md. Hasan babu, Nazir Saleheen, Lafifa Jamal, Sheikh Muhammad Sarwar, 2013, Approach to design a compact reversible low power binary comparator, IET Computers and Digital Technique, vol (8), Issue. 3, 129-139.
- H. Thapliyal and M. Srinivas. 2005. Novel Reversible 'TSG' Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU, Fifth International Conference on Information, Communications and Signal Processing, Bangkok, 1425-1429
- Rangaraju H G, Venugopal U, Muralidhara K N, Raja K B. 2010. Low Power Reversible Parallel Binary Adder / Subtractor, International journal of VLSI design & Communication Systems (VLSICS). vol. 1, no. 3, 1-12.
- Biswas, A. K. , Hasan, M. M. , Hasan, M. , Chowdhury, A. R. , & Hasan Babu. 2008. A novel approach to design BCD adder and Carry Skip BCD adder, 21st International Conference on VLSI Design, 566-571.
- Zhou, Rigui, Manqun Zhang, Qian Wu, and Yang Shi. 2012. Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates, International Journal of Electronics. v (99), no. 10, 1395-1414.
- Krishnaveni, D. , and Geetha Priya, M. 2010, A Novel Design of Reversible Serial and Parallel Adder/Subtractor, International Journal of Engineering Science and Technology, vol 3, 2280–2288.
Index Terms
Keywords