The week's pick
Reseach Article
Low Power Adder based ANN
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 118 - Number 10 |
| Year of Publication: 2015 |
| Authors: S N Prasad, S.y. Kulkarni |
10.5120/20778-3335
|
S N Prasad, S.y. Kulkarni . Low Power Adder based ANN. International Journal of Computer Applications. 118, 10 ( May 2015), 1-4. DOI=10.5120/20778-3335
Abstract
This paper presents an overview of datapath realizations of the Hardware neural network models which perform massive parallel operations for best results and real time applications. Digital implemented neural models processing element – adder with low power consumption is proposed for real-time multimedia applications. Proposed adder is illustrated in the 2-3-1 tree layer artificial neural network (ANN). Designs were modeled with Verilog HDL and implemented in FPGA domain by targeting the Virtex 7 device.
References
- Hassanien, Aboul-Ella, et al. "Computational intelligence in multimedia processing: foundation and trends. " Computational Intelligence in Multimedia Processing: Recent Advances. Springer Berlin Heidelberg, 2008. 3-49.
- Fang, Xuefeng "Small area, low power, mixed-mode circuits for hybrid neural network applications" Diss. Ohio University, 1994.
- C. A. Mead, Ismail M, "Analog VLSI Implementations of Neural Systems", Reading, MA: Addison-Wesley, 1989
- Chang, Chip-Hong, Jiangmin Gu, and Mingyan Zhang. "Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits. " Circuits and Systems I: Regular Papers, IEEE Transactions on 51. 10 (2004): 1985-1997.
- Murali, L. , D. Chitra, and T. Manigandan. "Low Power Adder Based Digital Filter for QRS Detector. " The Scientific World Journal 2014 (2014).
- Sharifi, Fazel, et al. "A Flexible Design for Optimization of Hardware Architecture in Distributed Arithmetic based FIR Filters. " RadioElectronics & Informatics 4 (2012) 25-30; arxiv: preprint arXiv:1403. 4554.
- Rashidi, B. ; Pourormazd, M. , "Design and implementation of low power digital FIR filter based on low power multipliers and adders on xilinx FPGA," Electronics Computer Technology (ICECT), 2011 3rd International Conference on , vol. 2, no. , pp. 18,22, 8-10 April 2011.
- W. S. McCulloch and W. H. Pitts, "A logic calculus of the ideas imminent in nervous activity," Bulletin of Mathematical Biophysics, vol. 5, pp. 115-133,1943.
- Sahin, Suhap, Yasar Becerikli, and Suleyman Yazici. "Neural network implementation in hardware using FPGAs. " Neural Information Processing. Springer Berlin Heidelberg, 2006.
- Dhafer r. Zaghar, "Reduction of the error in the hardware neural network", Al-khwarizmi Engineering Journal ,Vol. 3, No. 1 PP, 80-41 (2007)
- Neil H Weste and David M Harris, "CMOS VLSI Design- A Circuits & System Perspective", Pearson Education, 2008.
Index Terms
Keywords