CFP last date
20 June 2024
Reseach Article

Temperature Oriented Design of SRAM cell using CMOS Technology

by Rukkumani V, Devarajan N
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 122 - Number 15
Year of Publication: 2015
Authors: Rukkumani V, Devarajan N

Rukkumani V, Devarajan N . Temperature Oriented Design of SRAM cell using CMOS Technology. International Journal of Computer Applications. 122, 15 ( July 2015), 19-23. DOI=10.5120/21776-5046

@article{ 10.5120/21776-5046,
author = { Rukkumani V, Devarajan N },
title = { Temperature Oriented Design of SRAM cell using CMOS Technology },
journal = { International Journal of Computer Applications },
issue_date = { July 2015 },
volume = { 122 },
number = { 15 },
month = { July },
year = { 2015 },
issn = { 0975-8887 },
pages = { 19-23 },
numpages = {9},
url = { },
doi = { 10.5120/21776-5046 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T23:10:37.832205+05:30
%A Rukkumani V
%A Devarajan N
%T Temperature Oriented Design of SRAM cell using CMOS Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 122
%N 15
%P 19-23
%D 2015
%I Foundation of Computer Science (FCS), NY, USA

A set of components in a circuit which are called as modules or blocks are connected through interconnections called as 'wires'. Various computational techniques are used to calculate and minimize the area, power and speed. Single IC consists of number of Processing Elements (PE's), which works on various voltage ranges. Due to this the IC power consumption increases, thereby temperature of the chip also increases. The increased temperature in some parts is called as hotspots. The main goal of this paper is to focus on calculation of area, power and hotspot of SRAM memory circuit for 8T and 10T memory cell using Microwind. This may used to design of many complicated memory circuits for various temperature ranges. The Submicron Technology is widely used for designing any complex analog circuits.

  1. Hiroyuki Yamauchi 2010 A discussion on SRAM circuit design trend in deeper nanometer-scale technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18,no. 5,pp. 763-774.
  2. Hameem Shanavas and R. K. Gnanamurthy 2011 Wirelength minimization in partitioning and floorplanning using Evollutionary Algorithms. VLSI Design research article.
  3. Shah M Jahinuzzaman,, David J Rennie and Manoj Sachdev 2009 A soft error tolerant 10T SRAM bit-cell with differential read capability. IEEE Transactions on Nuclear Science, Vol. 56,No. 6,pp. 3768-3773.
  4. Meng-Fan Chang, Yung-Chi Chen and Chien-Fu Chen 2010 A 0. 45-V 300-MHz 10T flowthrough SRAM with expanded write/read stability and speed-area wise array for sub-0. 5-V chips. IEEE Transactions on Circuit and Systems-II:Express Briefs,Vol. 57,no. 12,pp. 980-985.
  5. Islam ,A and Hasan,M 2012 Leakage characterization of 10T SRAM cell. IEEE Transactions on Electron Devices,Vol. 59,no. 3,pp. 631-638.
  6. Verma N. and Chandrakasan A. P. 2007 65 nm 8T sub- SRAM employing sense-amplifier redundancy. in Proc. Int. Solid State Circuits Conf. , pp. 328–329.
  7. Grossar E. 2006 Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies. IEEE J. Solid-State Circuits,vol. 41,no. 11 ,pp. 2577-2588.
  8. M. Abramovich et al Digital System Testing and Testable Design. IEEE Press, 1990.
  9. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi,and M. Yoshimoto 2007 An area-conscious low-voltage oriented 8T-SRAM design under DVS environment. in Proc. VLSI Circuit Symp. pp. 14–16.
  10. Pavel Ghosh and Arunabha Sen 2010 Power Efficient Voltage Islanding for System-on-Chip from a floorplanning Perspective. In Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 39 – 44
  11. Simmy Hirkaney, Sandip Nemade, Vikash Gupta 2011 Power Efficient Design of Counter on 0. 12 Micron Technology. International Journal of Soft Computing and Engineering (IJSCE) Volume-1, Issue-1, pp. 19-23.
  12. K. Skadron, K. Sankaranarayanan, S. Velusamy, and D. Tarjan, and M. R. Stan, W. Huang 2004 Temperature-Aware Microarchitecture: Modeling and Implementation. ACM Transactions on Architecture and Code Optimization, To appear, 2004. Architecture (ISCA), pages 83–94.
  13. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan 2003 Temperature-aware microarchitecture. In Proc. ISCA-30, pages 2–13.
  14. Jason H Anderson & Farid N Najm 2004 Power estimation techniques for FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12,no. 10,pp. 1015-1027.
  15. B. Rajendra Nailk,Rameshwar Rao and Shefail 2011 Low-Area Low-Power and High-Speed TCAMS. International Conferences on VLSI, Communications& Instrumentation (ICVCI), Proceeding published by International Journal of Computer Applications,pp 4-10.
Index Terms

Computer Science
Information Sciences


Submicron technology 8T memory cell 10T cell hotspot