We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Reseach Article

Layout Design of Level Triggered Delay Register using 90 nm Technology

by Meenakshi Thakur, Rajesh Mehra
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 122 - Number 16
Year of Publication: 2015
Authors: Meenakshi Thakur, Rajesh Mehra
10.5120/21783-5060

Meenakshi Thakur, Rajesh Mehra . Layout Design of Level Triggered Delay Register using 90 nm Technology. International Journal of Computer Applications. 122, 16 ( July 2015), 10-13. DOI=10.5120/21783-5060

@article{ 10.5120/21783-5060,
author = { Meenakshi Thakur, Rajesh Mehra },
title = { Layout Design of Level Triggered Delay Register using 90 nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { July 2015 },
volume = { 122 },
number = { 16 },
month = { July },
year = { 2015 },
issn = { 0975-8887 },
pages = { 10-13 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume122/number16/21783-5060/ },
doi = { 10.5120/21783-5060 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:10:42.570066+05:30
%A Meenakshi Thakur
%A Rajesh Mehra
%T Layout Design of Level Triggered Delay Register using 90 nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 122
%N 16
%P 10-13
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This delay register design consist of 6 NMOS and 6 PMOS. The proposed delay register circuit has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis of modified layout has been done. Register has been designed using full automatic layout design, semicustom layout design and fullcustom layout design. Then the results of these different designs has been observed and compared in terms of area, delay and power. The simulation results show that circuit design of delay register saves the power by 17% when designed with fullcustom and area by 61. 8% when designed in semicustom.

References
  1. S. Matsumoto, H. J. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Test-circuit-based extraction of inter- and intra-chipMOSFET-performance variations for analog-design reliability," Proc. CICC, pp. 582–585, May 2001.
  2. Rachit Manchanda, Rajesh Mehra , "Low Propagation Delay Design of 3-bit ripple counter on 0. 12 Micron Technology", International Journal of Research in Computer Applications and Robotics,Vol. 1, Issue. 2, pp. 7-15,March-April 2013.
  3. Neil H. E. Weste, David Harris and Ayan Banaerjee, "CMOS VLSI design " pp. 9-10.
  4. Eitenne Sicard,Sonia Delmas Bendhia, Basic of CMOS Cell Design,TATA Mc GRAW-Hill. I. S. Jacobs and C. P. Bean, "Fine particles, thin films and exchange anisotropy," in Magnetism, Vol. III, G. T. Rado and H. Suhl, Eds. New York, Academic, pp. 271-350, 1963.
  5. K. Rajasri, A. Bharathi, M. Manikandan, "Performance of Flip-Flop using 22nm CMOS Technology", International Journal of Innovative Research in Computer and Communication Engineering, Vol. 2, Issue 8,pp. 5272-5276,2014.
  6. Prashant Upadhyay and Rajesh Mehra, "Low Power Design of an SRAM Cell for Portable Devices'', International Conference on Computer & Communication Technology (ICCCT ),pp. 255-259,2010.
  7. Pushpa saini, Rajesh Mehra, "Leakage Power Reduction in CMOS VLSI Circuits", International Journal of Computer Applications, Vol. 55, No. 8, pp. 42-48, 2012.
  8. Subodh Wairya,Rajendera Kumar Nagaria, Sudarshan tiwari, "New design methodologies for high speed mix mode full adder circuits", International Journal of VLSI and communication systems,Vol 2, Issue 2, pp. 78-98,2011.
  9. Subodh Wairya,Rajendera Kumar Nagaria, Sudarshan tiwari, "Comparitive performance analysis of XOR/XNOR Function based CMOS full adder circuit for low voltage VLSI design'', International Journal of VLSI and Communication systems,pp 221-242,2012.
  10. Boyer, aboulhamid, "optimal design of synchronous circuits using pipelining techniques'', International conference on Computer Design: VLSI in Computers and Processors(ICCD), pp. 62-67,1998.
  11. Kumar,V. M Senthil, "Design of delay buffer using shift registers for asynchronous data sampling" International conference on Power and Computing Technologies(ICCPCT), pp. 1748-1752,2014.
  12. M. Morris Mano, Digital Design, PHI, pp. 57,171.
  13. Wikipedia. org/wiki/flip-flop.
  14. Akhilesh Verma, Rajesh Mehra, "Design and Analysis of Conventional and Rationed CMOS logic", IOSR of VLSI and signal processing (IOSR-JVSR), Vol 2 , Issue 2, pp. 25-29, 2013.
Index Terms

Computer Science
Information Sciences

Keywords

Pass Transistor CMOS Power Dissipation NMOS PMOS .