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Reseach Article

Layout Design of Level Triggered Delay Register using 90 nm Technology

by Meenakshi Thakur, Rajesh Mehra
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 122 - Number 16
Year of Publication: 2015
Authors: Meenakshi Thakur, Rajesh Mehra
10.5120/21783-5060

Meenakshi Thakur, Rajesh Mehra . Layout Design of Level Triggered Delay Register using 90 nm Technology. International Journal of Computer Applications. 122, 16 ( July 2015), 10-13. DOI=10.5120/21783-5060

@article{ 10.5120/21783-5060,
author = { Meenakshi Thakur, Rajesh Mehra },
title = { Layout Design of Level Triggered Delay Register using 90 nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { July 2015 },
volume = { 122 },
number = { 16 },
month = { July },
year = { 2015 },
issn = { 0975-8887 },
pages = { 10-13 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume122/number16/21783-5060/ },
doi = { 10.5120/21783-5060 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:10:42.570066+05:30
%A Meenakshi Thakur
%A Rajesh Mehra
%T Layout Design of Level Triggered Delay Register using 90 nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 122
%N 16
%P 10-13
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This delay register design consist of 6 NMOS and 6 PMOS. The proposed delay register circuit has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis of modified layout has been done. Register has been designed using full automatic layout design, semicustom layout design and fullcustom layout design. Then the results of these different designs has been observed and compared in terms of area, delay and power. The simulation results show that circuit design of delay register saves the power by 17% when designed with fullcustom and area by 61. 8% when designed in semicustom.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Pass Transistor CMOS Power Dissipation NMOS PMOS .