Area Efficient Layout Design of CMOS Comparator using PTL Logic
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10.5120/21784-5065 |
Jyoti and Rajesh Mehra. Article: Area Efficient Layout Design of CMOS Comparator using PTL Logic. International Journal of Computer Applications 122(16):14-17, July 2015. Full text available. BibTeX
@article{key:article,
author = {Jyoti and Rajesh Mehra},
title = {Article: Area Efficient Layout Design of CMOS Comparator using PTL Logic},
journal = {International Journal of Computer Applications},
year = {2015},
volume = {122},
number = {16},
pages = {14-17},
month = {July},
note = {Full text available}
}
Abstract
Comparator is a very useful combinational logic circuit. In this paper performance analysis of CMOS Comparator and PTL logic design has been shown. In the design of integrated circuits, several logic families is being used which is described by Pass Transistor Logic (PTL). It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. The layout of 2-bit comparator is developed using automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is optimized manually. The result shows that semi-custom layout of PTL logic consumes 35% less area as compared to CMOS logic design to provide area efficient solution.
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