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Reseach Article

Area Efficient Layout Design of CMOS Comparator using PTL Logic

by Jyoti, Rajesh Mehra
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 122 - Number 16
Year of Publication: 2015
Authors: Jyoti, Rajesh Mehra
10.5120/21784-5065

Jyoti, Rajesh Mehra . Area Efficient Layout Design of CMOS Comparator using PTL Logic. International Journal of Computer Applications. 122, 16 ( July 2015), 14-17. DOI=10.5120/21784-5065

@article{ 10.5120/21784-5065,
author = { Jyoti, Rajesh Mehra },
title = { Area Efficient Layout Design of CMOS Comparator using PTL Logic },
journal = { International Journal of Computer Applications },
issue_date = { July 2015 },
volume = { 122 },
number = { 16 },
month = { July },
year = { 2015 },
issn = { 0975-8887 },
pages = { 14-17 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume122/number16/21784-5065/ },
doi = { 10.5120/21784-5065 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:10:43.237438+05:30
%A Jyoti
%A Rajesh Mehra
%T Area Efficient Layout Design of CMOS Comparator using PTL Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 122
%N 16
%P 14-17
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Comparator is a very useful combinational logic circuit. In this paper performance analysis of CMOS Comparator and PTL logic design has been shown. In the design of integrated circuits, several logic families is being used which is described by Pass Transistor Logic (PTL). It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. The layout of 2-bit comparator is developed using automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is optimized manually. The result shows that semi-custom layout of PTL logic consumes 35% less area as compared to CMOS logic design to provide area efficient solution.

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Index Terms

Computer Science
Information Sciences

Keywords

CMOS technology Layout Performance analysis logic circuits PTL