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Design of Low Power, High Gain PLL using CS-VCO on 180nm Technology

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International Journal of Computer Applications
© 2015 by IJCA Journal
Volume 122 - Number 18
Year of Publication: 2015
Authors:
Anshul Agrawal
Rajesh Khatri
10.5120/21802-5110

Anshul Agrawal and Rajesh Khatri. Article: Design of Low Power, High Gain PLL using CS-VCO on 180nm Technology. International Journal of Computer Applications 122(18):26-31, July 2015. Full text available. BibTeX

@article{key:article,
	author = {Anshul Agrawal and Rajesh Khatri},
	title = {Article: Design of Low Power, High Gain PLL using CS-VCO on 180nm Technology},
	journal = {International Journal of Computer Applications},
	year = {2015},
	volume = {122},
	number = {18},
	pages = {26-31},
	month = {July},
	note = {Full text available}
}

Abstract

This paper investigates the design and performance of the PLL (Phase Locked Loop). The proposed PLL designed with PFD (Phase Frequency Detector), CP (Charge Pump), first order Low Pass Filter and CS-VCO (Current Starved-Voltage Control Oscillator), in this paper the designed PFD used for proposed PLL is free from dead zone. The VCO used for the designed PLL shows larger tuning range and high gain as compares to previous work, i. e. tuning range (167MHz – 1. 711GHz) and VCO gain (2. 21GHz/V or 13. 875*109 radians/s*V). In the proposed work, the designed PLL has higher pull-in range 980MHz (20MHz – 1GHz) with maximum jitter 9. 8ps. Power dissipation for proposed PLL system is low, i. e. 277. 2 µW with maximum pull-in time is 265ns at 1GHz. The proposed PLL circuit is implemented on CADENCE UMC0. 18um process technology file with supply voltage 1. 8V. All simulations are done using cadence spectre simulator.

References

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