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Design of Low Power, High Gain PLL using CS-VCO on 180nm Technology

International Journal of Computer Applications
© 2015 by IJCA Journal
Volume 122 - Number 18
Year of Publication: 2015
Anshul Agrawal
Rajesh Khatri

Anshul Agrawal and Rajesh Khatri. Article: Design of Low Power, High Gain PLL using CS-VCO on 180nm Technology. International Journal of Computer Applications 122(18):26-31, July 2015. Full text available. BibTeX

	author = {Anshul Agrawal and Rajesh Khatri},
	title = {Article: Design of Low Power, High Gain PLL using CS-VCO on 180nm Technology},
	journal = {International Journal of Computer Applications},
	year = {2015},
	volume = {122},
	number = {18},
	pages = {26-31},
	month = {July},
	note = {Full text available}


This paper investigates the design and performance of the PLL (Phase Locked Loop). The proposed PLL designed with PFD (Phase Frequency Detector), CP (Charge Pump), first order Low Pass Filter and CS-VCO (Current Starved-Voltage Control Oscillator), in this paper the designed PFD used for proposed PLL is free from dead zone. The VCO used for the designed PLL shows larger tuning range and high gain as compares to previous work, i. e. tuning range (167MHz – 1. 711GHz) and VCO gain (2. 21GHz/V or 13. 875*109 radians/s*V). In the proposed work, the designed PLL has higher pull-in range 980MHz (20MHz – 1GHz) with maximum jitter 9. 8ps. Power dissipation for proposed PLL system is low, i. e. 277. 2 µW with maximum pull-in time is 265ns at 1GHz. The proposed PLL circuit is implemented on CADENCE UMC0. 18um process technology file with supply voltage 1. 8V. All simulations are done using cadence spectre simulator.


  • Abdul Majeed, K. K. and Binsu J. Kailath, "Low power, High Frequency, Free Dead Zone PFD for a PLL Design", IEEE 2013.
  • Ashish Mishra, Gaurav Kr. Sharma and D. Boolchandani, "Performance Analysis of Power Optimal PLL Design Using Five-Stage CS-VCO in 180nm", International Conference on Signal Propagation and Computer Technology (ICSPCT), IEEE 2014.
  • S. Aditya and S. Moorthi, "A Low Jitter Wide Tuning range Phase Locked Loop with Low Power Consumption in 180nm CMOS Technology", Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), IEEE 2013.
  • B. Razavi, "Design of Analog CMOS Integrated Circuits", McGraw-Hill, 2002.
  • Kim, Seung-Hoon and Sang-Bock Cho, "Low Phase noise and Fast Locking PLL Frequency Synthesizer for a 915MHz ISM Band", In Integrated Circuit, 2007, ISIC07 International Symposium on pp. 592-595, IEEE 2007.
  • Xiaoliang Xu, Huihua Liu and Siyan Ao, "Design of low phase noise and fast locking PLL frequency synthesizer. " In International Conference on Electric Information and Control Engineering on pp. 4113-4116, 2011.
  • S. Verma, J. Xu and T. H. Lee, "A Multiply-by-3 Coupled Ring Oscillator for Low power Frequency Synthesis", IEEE J. Solid State Circuits on pp. 709-713, 2004.
  • Gauri Shankar Singh, Devesh Singh and S. Moorthi, "Low Power Low Jitter Phase Locked Loop for High Speed Clock Generation", Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PRIMEASIA), December 2012.
  • Patri Sreehari, P. Devulapalli, Dhananjay Kewale, Omkar Asbe and KSR Krishna Prasad, "Power Optimized PLL Implementation IN 180nm CMOS Technology", IEEE 2014.
  • Analog Integrated Circuits by David Johns and Ken Martin.
  • Principles of CMOS VLSI Design by Neil H. E. Weste and Kamran Eshraghian.