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32 nm Gate Length FinFET: Impact of Doping

International Journal of Computer Applications
© 2015 by IJCA Journal
Volume 122 - Number 6
Year of Publication: 2015
Neha Somra
Ravinder Singh Sawhney

Neha Somra and Ravinder Singh Sawhney. Article: 32 nm Gate Length FinFET: Impact of Doping. International Journal of Computer Applications 122(6):11-14, July 2015. Full text available. BibTeX

	author = {Neha Somra and Ravinder Singh Sawhney},
	title = {Article: 32 nm Gate Length FinFET: Impact of Doping},
	journal = {International Journal of Computer Applications},
	year = {2015},
	volume = {122},
	number = {6},
	pages = {11-14},
	month = {July},
	note = {Full text available}


FinFET, a self–aligned double-gate MOSFET structure has been agreed upon to eliminate the short channel effects. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1. 5V and Tox=5nm. We elucidate the impact of doping concentration on the Performance of n-channel 32nm gate length FinFET at 22nm width. The drain current increases gradually when donor ion concentration in source/drain regions increases to 7e20 cm-3. Adding opposite type of source/drain impurity or decreasing acceptor ion concentration in channel further improves the performance of FinFET.


  • Maryam Nezafat1, Omid Zeynali2, Daruosh Masti3 "Negative Resistance Region 10nm Gate Length on FinFET", Journal of Modern Physics, 2014, 5, 1117-1123 Published Online July 2014 in SciRes.
  • Xuejue Huang et al. "Sub 50-nm FinFET: PMOS", International Electron Devices Meeting-IEDM, 1999, DOI: 10. 1109/IEDM. 1999. 823848
  • F. Daugea, J. Preteta,c, S. Cristoloveanua, A. Vandoorenb, L. Mathewb, J. Jomaaha, B. -Y. Nguyenb" coupling effects and channels separation in FinFETs" aIMEP (UMR CNRS/INPG/UJF), ENSERG BP 257, 38016 Grenoble Cedex1, France; bMotorola, Digital DNA Lab. , 3501 Ed Bluestein Blvd, Austin, TX 78721, USA; cSTMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France.
  • Md. Alamgir hossain "A Qualitative Approach on FinFET Devices Characteristics", Much Lower off?state Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
  • Mahender Veshala, Ramchander Jatooth, Kota Rajesh Reddy "Reduction of Short-Channel Effects in FinFET" International Journal of Engineering and Innovative Technology (IJEIT) Volume 2, Issue 9, March 2013.
  • Bin Yu et al. "FinFET Scaling to 10nm Gate Length", Strategic Technology, Advanced Micro Devices, Inc. , Sunnyvale, CA 94088, USA Department of EECS, University of California, Berkeley, CA 94720, USA, VLSI Technology Digest of Technical Papers, IEEE, 2002, pp. 251-254.
  • Vikram V. Iyengar, Anil Kottantharayil "Extraction of the Top and Sidewall Mobility in FinFETs and the Impact of Fin-Patterning Processes and Gate Dielectrics on Mobility IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 5, MAY 2007.
  • Suman Latatripathi, Ramanuj Mishra, Sandeep Mishra, Virendra Pratap Yadav & R. A. Mishra "Performance comparison of bulk FinFET with SOI FinFET in nano-scale regime" International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231- 5969, Vol-2, ISS-2,3,4, 2012.