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Reseach Article

32 nm Gate Length FinFET: Impact of Doping

by Neha Somra, Ravinder Singh Sawhney
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 122 - Number 6
Year of Publication: 2015
Authors: Neha Somra, Ravinder Singh Sawhney

Neha Somra, Ravinder Singh Sawhney . 32 nm Gate Length FinFET: Impact of Doping. International Journal of Computer Applications. 122, 6 ( July 2015), 11-14. DOI=10.5120/21703-4816

@article{ 10.5120/21703-4816,
author = { Neha Somra, Ravinder Singh Sawhney },
title = { 32 nm Gate Length FinFET: Impact of Doping },
journal = { International Journal of Computer Applications },
issue_date = { July 2015 },
volume = { 122 },
number = { 6 },
month = { July },
year = { 2015 },
issn = { 0975-8887 },
pages = { 11-14 },
numpages = {9},
url = { },
doi = { 10.5120/21703-4816 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T23:09:51.241524+05:30
%A Neha Somra
%A Ravinder Singh Sawhney
%T 32 nm Gate Length FinFET: Impact of Doping
%J International Journal of Computer Applications
%@ 0975-8887
%V 122
%N 6
%P 11-14
%D 2015
%I Foundation of Computer Science (FCS), NY, USA

FinFET, a self–aligned double-gate MOSFET structure has been agreed upon to eliminate the short channel effects. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1. 5V and Tox=5nm. We elucidate the impact of doping concentration on the Performance of n-channel 32nm gate length FinFET at 22nm width. The drain current increases gradually when donor ion concentration in source/drain regions increases to 7e20 cm-3. Adding opposite type of source/drain impurity or decreasing acceptor ion concentration in channel further improves the performance of FinFET.

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Index Terms

Computer Science
Information Sciences


FinFETs CMOS Drain Induced barrier lowering Silicon-on-insulator