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Compact, High Speed and Low power Decoders for Future Generation System Building

by Prameela Kumari N., K.S. Gurumurthy
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 123 - Number 7
Year of Publication: 2015
Authors: Prameela Kumari N., K.S. Gurumurthy
10.5120/ijca2015905392

Prameela Kumari N., K.S. Gurumurthy . Compact, High Speed and Low power Decoders for Future Generation System Building. International Journal of Computer Applications. 123, 7 ( August 2015), 30-36. DOI=10.5120/ijca2015905392

@article{ 10.5120/ijca2015905392,
author = { Prameela Kumari N., K.S. Gurumurthy },
title = { Compact, High Speed and Low power Decoders for Future Generation System Building },
journal = { International Journal of Computer Applications },
issue_date = { August 2015 },
volume = { 123 },
number = { 7 },
month = { August },
year = { 2015 },
issn = { 0975-8887 },
pages = { 30-36 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume123/number7/21973-2015905392/ },
doi = { 10.5120/ijca2015905392 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:12:03.525104+05:30
%A Prameela Kumari N.
%A K.S. Gurumurthy
%T Compact, High Speed and Low power Decoders for Future Generation System Building
%J International Journal of Computer Applications
%@ 0975-8887
%V 123
%N 7
%P 30-36
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Electronic system building has become highly competitive from the point of reducing area, power and increasing the speed. To address these issues, many technologies are being tried. Quantum Dot Cellular Automation is one such technology. This technology is in its infant state as far as its physical implementation and verification are concerned. However the researchers have come out with theoretical models and proposed many compact, fast and low power dissipating digital blocks. Decoders are one of the standard combinational modules used as the basic building blocks for efficient digital system design. Here in this paper we implement decoders in QCA using different techniques and analyze them with respect to area, time and energy. From the implementation and simulation results obtained using QCADESIGNER version 2.0.3 we have observed that, the 2:4 decoders implemented with and without the enable input using both single layer and multilayer techniques utilize minimum area, time and energy.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Quantum Dot Cellular Automata (QCA) Decoder Coincident Decoding Tree Decoding Universal Module.

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