Call for Paper - January 2023 Edition
IJCA solicits original research papers for the January 2023 Edition. Last date of manuscript submission is December 20, 2022. Read More

FinFET based 6T SRAM Cell for Nanoscaled Technologies

Print
PDF
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2015
Authors:
Lalit Mohan Dani, Gurmohan Singh, Manjit Kaur
10.5120/ijca2015906573

Lalit Mohan Dani, Gurmohan Singh and Manjit Kaur. Article: FinFET based 6T SRAM Cell for Nanoscaled Technologies. International Journal of Computer Applications 127(13):5-10, October 2015. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

@article{key:article,
	author = {Lalit Mohan Dani and Gurmohan Singh and Manjit Kaur},
	title = {Article: FinFET based 6T SRAM Cell for Nanoscaled Technologies},
	journal = {International Journal of Computer Applications},
	year = {2015},
	volume = {127},
	number = {13},
	pages = {5-10},
	month = {October},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}
}

Abstract

FinFET is a non planar modeling device for small size transistors (less than 45nm) will replace traditional planar MOSFETs because of superior ability to control short channel effects, off-state leakage current, power dissipation and propagation delay. Static random access memories (SRAMs) consume nearly 94% of chip area in most present system-on-chip (SoC) circuits. In this paper, a standard 6T SRAM cell has been designed using dual gate FinFET transistors and its performance for read/write operation is analyzed in terms of average power consumption, propagation delay, power delay product (PDP) and static noise margin (SNM) for nanoscaled technologies. A comprehensive comparison is carried out with conventional 6T CMOS SRAM cell for 45nm, 32nm and 16nm nanoscaled technologies. A reduction in power delay product by 87.5%, 88.8% and 99.1% in read operation and 90.4%, 89.2% and 96.9% in write operation of FinFET based SRAM cell at 45nm, 32nm and 16nm technology nodes respectively as compared to 6T CMOS SRAM cell. Also an improvement in static noise margin by 27.5%, 31.5% and 8.9% of FinFET based SRAM cell is obtained at 45nm, 32nm and 16nm technology nodes respectively.

References

  1. Debajit Bhattacharya and Niraj K. Jha, “FinFETs: From Devices to Architectures,” Advances in Electronics, vol. 2014, Article ID 365689, 21 pages, 2014. doi:10.1155/2014/365689
  2. Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolić, “FinFET-Based SRAM Design” ,Proceedings of the 2005 International Symposium on Low Power Electronics and Design (ISLPED '05), pp. 2-7, 2005.
  3. Zheng Guo, Andrew Carlson, Liang-Teck Pang, Kenneth T. Duong, Tsu-Jae King Liu, and Borivoje Nikolic, “Large Scale SRAM Variability Characterization in 45 nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 11, Nov. 2009.
  4. Karishma Bajaj, Manjit Kaur, Gurmohan Singh,” Design and Analysis of Hybrid CMOS SRAM Sense Amplifier, International Journal of Electronics and Computer Science Engineering, Volume-1, Number-2, pp. 718-726, 2012.
  5. Balwant Raj, Anita Suman, Gurmohan Singh, “Analysis of Power Dissipation in DRAM Cells Design for Nanoscale Memories”, International Journal of Information Technology & Knowledge Management, July-December 2009, Volume-2,No. 2,pp. 371-374.
  6. Benton H. Calhoun, Yu Cao, Xin Li, “Performance Evaluation of Emerging Devices Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, in Proceedings of the IEEE, 2008, vol. 96, no. 2, pp.342-365.
  7. Wenwei Yang, Zhiping Yu, Senior Member, IEEE, and Lilin Tian, “Scaling theory for FinFETs based on 3D effects investigation”, IEEE transactions on electron devices, vol. 54, no. 5, may 2007.
  8. B. Raj, A. K. Saxena and S. Dasgupta, “Quantum Mechanical Analytical Modeling of Nanoscale DG FinFET: Evaluation of Potential, Threshold Voltage and Source/Drain Resistance ” Elsevier’s Journal of Material Science in Semiconductor Processing, Vol. 16, issue 4, pp. 1131- 1137, 2013.
  9. B. Raj, A. K. Saxena and S. Dasgupta, “Analytical Modeling for the Estimation of Leakage Current and Subthreshold Swing Factor of Nanoscale Double Gate FinFET Device” Microelectronics International, UK, Vol. 26, pp. 53-63, 2009.
  10. B. Raj, A. K. Saxena and S. Dasgupta, “A Compact Drain Current and Threshold Voltage Quantum Mechanical Analytical Modeling for FinFETs” Journal of Nanoelectronics and Optoelectronics (JNO), USA, Vol. 3, no. 2, pp. 163-170, 2008.
  11. B. Yu, L. Chang, S. Ahmed et al., “FinFET scaling to 10 nm gate length,” in Proceedings of the IEEE International Devices Meeting (IEDM '02), pp. 251–254, San Francisco, Calif, USA, December 2002.
  12. B. Raj, A. K. Saxena and S. Dasgupta, “Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance metric, Process variation, Underlapped FinFET and Temperature effect” IEEE Circuits and System Magazine, vol. 11, issue 2, pp. 38- 50, 2011.
  13. Ming-Long Fan; Yu-Sheng Wu; Hu, V.P.-H.; Chien-Yu Hsieh; Pin Su; Ching-Te Chuang, "Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach,"  IEEE Transactions on Electron Devices,Vol.58, no.3, pp. 609,616, Mar. 2011.
  14. Lourts Deepak, A.; Dhulipalla, L., "Design and implementation of 32nm FINFET based 4×4 SRAM cell array using 1-bit 6T SRAM," International Conference on Nanoscience, Engineering and Technology (ICONSET), 2011, vol.177, no.180, pp. 28-30 Nov. 2011.
  15. Rahaman, M.; Mahapatra, R., "Design of a 32nm independent gate FinFET based SRAM cell with improved noise margin for low power application," International conference on electronics and communication systems (ICECS), 2014, Vol.1, no.5, pp.13-14, Feb. 2014.
  16. Z. Guo, Shriram B., Radu Z., T. King, B. Nikolic, “FinFET based Design for Robust Nanoscale SRAM”, Proceeding of the international symposium on Low Power Electronics and design, pp 2-7, 2005.
  17. A. N. Bhoj and N. K. Jha, “Design of logic gates and flip-flops in high-performance FinFET technology”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 11, pp. 1975–1988, 2013.

Keywords

CMOS, FinFET, SRAM, DRAM, SNM, PDP, SoC, RDF, SCE