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An Efficient VLSI Architecture for Carry Select Adder Without Multiplexer
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 127 - Number 9 |
| Year of Publication: 2015 |
| Authors: Deepak Kumar Patel, Raksha Chouksey, Minal Saxena |
10.5120/ijca2015906492
|
Deepak Kumar Patel, Raksha Chouksey, Minal Saxena . An Efficient VLSI Architecture for Carry Select Adder Without Multiplexer. International Journal of Computer Applications. 127, 9 ( October 2015), 37-40. DOI=10.5120/ijca2015906492
Abstract
High performance digital adder with less power consumption and reduced area is a fundamental design issues for advanced processors. Carry Select Adder (CSA) is one of the fastest adder used in many processors to perform fast arithmetic function. Many different adder architecture designs have been developed to increase the efficiency of the adder. As we know millions of instructions per second are performed in microprocessors. So, speed of operation is the most important constraint to be considered while designing. Due to which high speed adder and multiplier architecture plays an important role in many applications. In this paper, we proposed a technique for designing of carry select adder without using multiplexer. Verification of CSA architecture is done through design and implementation of 16, 32 and 64 bit. Comparison is done with existing structure of adder and proves the efficiency of our proposed design. These designs are implemented on Xilinx device family.
References
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