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Reseach Article

A Robust 10T SRAM Cell with Enhanced Read Operation

by Sayeed Ahmad, Naushad Alam, Mohd. Hasan
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 129 - Number 2
Year of Publication: 2015
Authors: Sayeed Ahmad, Naushad Alam, Mohd. Hasan
10.5120/ijca2015906751

Sayeed Ahmad, Naushad Alam, Mohd. Hasan . A Robust 10T SRAM Cell with Enhanced Read Operation. International Journal of Computer Applications. 129, 2 ( November 2015), 7-12. DOI=10.5120/ijca2015906751

@article{ 10.5120/ijca2015906751,
author = { Sayeed Ahmad, Naushad Alam, Mohd. Hasan },
title = { A Robust 10T SRAM Cell with Enhanced Read Operation },
journal = { International Journal of Computer Applications },
issue_date = { November 2015 },
volume = { 129 },
number = { 2 },
month = { November },
year = { 2015 },
issn = { 0975-8887 },
pages = { 7-12 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume129/number2/23043-2015906751/ },
doi = { 10.5120/ijca2015906751 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:22:18.560271+05:30
%A Sayeed Ahmad
%A Naushad Alam
%A Mohd. Hasan
%T A Robust 10T SRAM Cell with Enhanced Read Operation
%J International Journal of Computer Applications
%@ 0975-8887
%V 129
%N 2
%P 7-12
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents a new 10T SRAM cell that has enhanced read speed along with good read and write stability. While the read access time of the proposed cell is 0.72x and 0.83x smaller as compared to the two most popular 10T SRAM cells at 500C; the read SNM is 1.16x and 1.05x higher compared to existing 10T cells. Though the read-write power of the proposed cell is higher with respect to the existing 10T cells; nevertheless, it consumes lower power as compared to the conventional 6T cell. Layout using 45nm technology rule shows that the proposed cell consumes 15% smaller area as compared to popular Schmitt-trigger based 10T SRAM cell. Also, the results of Monte-Carlo simulation show that the proposed cell is more robust against process variations. Therefore, the proposed 10T SRAM cell can be used where the speed and robustness are the primary requirements.

References
  1. International Technology Roadmap for Semiconductors (ITRS). [Online]. Available:http://public.itrs.net
  2. J. S. Rad, M. Guthaus, and R. Hughey, “Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield”, IEEE Access, Vol. 2, pp. 577-601, 2014.
  3. J. P. Kulkarni, K. Kim, and K. Roy, “A 160 mV robust Schmitt trigger based subthresholdSRAM,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2303–2313, 2007.
  4. B. H. Calhoun, and A. P. Chandrakasan, “A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation”, IEEE Journal of Solid-State Circuits, , Vol. 42, No. 3, pp. 680-688, 2007.
  5. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits:A Design Perspective, 2nd ed. New Delhi, India: Prentice-Hall,2005.
  6. E. Grossar, M. Stucchi, K. Maex, W. Dehaene, “Read stability and write-ability analysis of SRAM cells for nanometer technologies” , IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2577–2588, 2006.
  7. A. Islam and Mohd. Hasan, “Leakage Characterization of 10T SRAM Cell,” IEEE Transactions on Electron Devices, vol. 59, no. 3, pp. 631–638, 2012.
  8. Roghayeh Saeidi, M. Sharifkhani and K.Hajsadeghi, “A Subthreshold Symmetric SRAM Cell With High Read Stability”, IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 61, no. 1, pp. 26-30, 2014.
  9. Synopsys HSPICE User guide, Simulation & Analysis, 2012.
  10. Berkeley Predictive Technology Model, 2013. Website, 〈http://www.eas.asu.edu/~ptm〉.
  11. A. Islam, and Mohd. Hasan, “A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM Cell”, Microelectronics Reliability, vol. 52, No. 2, pp. 405-411, 2012.
  12. E. Seevinck, F.J. List, J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells”, IEEE Journal of Solid-State Circuits, vol. 22, no. 5, pp. 748–754, 1987.
  13. A. E. Carlson, “Device and circuit techniques for reducing variation in nanoscale SRAM,” Ph.D. dissertation, University of California Berkeley,Berkeley, CA, May 2008.
  14. Z. Guo, A. Carlson, L.-T. Pang, K. T. Duong, T.-J. K. Liu, and B. Nikolic, “Large-scale SRAM variability characterization in 45 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3174–3192, Nov. 2009.
  15. O. Okobiah, S. P. Mohanty, E. Kougianos, and M. Poolakkaparambil, “Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective”, . Proceedings of the 21st edition of the Great Lakes Symposium on VLSI, pp. 145-150, 2011.
  16. S. Lin, Y.-B. Kim, and F. Lombardi, “Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability,” Integr. VLSI Jornal, vol. 43, no. 2, pp. 176–187, Apr. 2010.
  17. G. Pasandi, S. M. Fakhraie, “A 256-kb 9T near-threshold SRAM with 1k cells per bitline and enhanced write and read operations”, IEEE Transactions on VLSI Systems, vol. PP, no. 99, pp. 1-9, 2015.
  18. Samar K. Saha, “Compact MOSFET modeling for process-variability aware VLSI circuit design”, IEEE Access, vol. 2, pp. 104-115, 2014.
Index Terms

Computer Science
Information Sciences

Keywords

6T-SRAM 10T-SRAM Access Time Monte-Carlo Simulation Noise Margin Variability.