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Distributed Arithmetic based Low-Power LMS Adaptive FIR Filter Design
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 132 - Number 16 |
| Year of Publication: 2015 |
| Authors: Wasim Maroofi, Lalit Jain |
10.5120/ijca2015907688
|
Wasim Maroofi, Lalit Jain . Distributed Arithmetic based Low-Power LMS Adaptive FIR Filter Design. International Journal of Computer Applications. 132, 16 ( December 2015), 10-14. DOI=10.5120/ijca2015907688
Abstract
Adaptive filtering forms a significant class of DSP algorithms employed in several hand held mobile devices for applications like echo cancellation, signal de-noising, and channel equalization. This paper presents a different pipelined architecture for low-power implementation of Adaptive filter based on distributed arithmetic (DA). The traditional adder-based shift accumulation for Distributed Arithmetic based computation of inner-product is swapped by conditional signed carry-save accumulation. A fast bit clock is employed only for carry-save accumulation which results in reduction of power consumption in the proposed design, while use of a much slower bit clock is used for rest of the operations. It contains the smaller Look-Up Table (LUT), same quantity of multiplexers and almost half the number of adders in comparison to the existing Distributed Arithmetic-based design. By changing the inner block, a reduction in power consumption is aimed at. So the previous DA-based adaptive filter in average for filter lengths N=4 and N=16 have been implemented.
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