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Design and Simulation of 2:4 Decoder using Hybrid Set-MOS Technology

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Daya Nand Gupta, S. R. P. Sinha

Daya Nand Gupta and S R P Sinha. Article: Design and Simulation of 2:4 Decoder using Hybrid Set-MOS Technology. International Journal of Computer Applications 133(1):1-7, January 2016. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

	author = {Daya Nand Gupta and S. R. P. Sinha},
	title = {Article: Design and Simulation of 2:4 Decoder using Hybrid Set-MOS Technology},
	journal = {International Journal of Computer Applications},
	year = {2016},
	volume = {133},
	number = {1},
	pages = {1-7},
	month = {January},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}


Single Electron Transistor (SET) is an advanced technology for future low power VLSI devices. SET has high integration density and a low power consumption device. While building logic circuits that comprise only of SETs, it is observed that the gate voltage at the input must be higher than the power supply of SET for better switching characteristics. This limitation of SET in the power and gate supply voltages makes it practically inappropriate to build circuits. An approach to overcome this problem, hybridization of SET and CMOS transistor is implemented. In this paper, different types of hybrid SET-MOS circuits are designed such as inverter and NAND gate and by using above two circuits, 2:4 hybrid SET-MOS decoder is designed and implemented. All the circuits are verified by means of PSpice simulation software version 16.5.


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Single Electron Transistor (SET), CMOS, Coulomb Blockade, Orthodox Theory, Hybrid SET-MOS, Decoder, Pspice