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Comparative Analysis of Low Leakage SRAM Cell at 32nm Technology

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Authors:
Jaspreet Kaur, Candy Goyal
10.5120/ijca2016908081

Jaspreet Kaur and Candy Goyal. Article: Comparative Analysis of Low Leakage SRAM Cell at 32nm Technology. International Journal of Computer Applications 133(12):50-56, January 2016. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

@article{key:article,
	author = {Jaspreet Kaur and Candy Goyal},
	title = {Article: Comparative Analysis of Low Leakage SRAM Cell at 32nm Technology},
	journal = {International Journal of Computer Applications},
	year = {2016},
	volume = {133},
	number = {12},
	pages = {50-56},
	month = {January},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}
}

Abstract

Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are the most important criteria for the fabrication of DSP systems. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, toward higher storage densities. This paper deals with design of low power static random-access memory (RAM) cells and peripheral circuits for standalone RAMs, in 32nm focusing on stable operation and reduced leakage power dissipation. The work is carried out on Tanner Tool version 13 at 32nm technology.

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Keywords

SRAM, VLSI, Leakage Power Dissipation, Static Power, Dynamic Power.