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A Survey Paper on Implementing MTCMOS Technique in Full Subtractor Circuit

by Tanvi Nagariya, Braj Bihari Soni
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 138 - Number 5
Year of Publication: 2016
Authors: Tanvi Nagariya, Braj Bihari Soni
10.5120/ijca2016908824

Tanvi Nagariya, Braj Bihari Soni . A Survey Paper on Implementing MTCMOS Technique in Full Subtractor Circuit. International Journal of Computer Applications. 138, 5 ( March 2016), 1-4. DOI=10.5120/ijca2016908824

@article{ 10.5120/ijca2016908824,
author = { Tanvi Nagariya, Braj Bihari Soni },
title = { A Survey Paper on Implementing MTCMOS Technique in Full Subtractor Circuit },
journal = { International Journal of Computer Applications },
issue_date = { March 2016 },
volume = { 138 },
number = { 5 },
month = { March },
year = { 2016 },
issn = { 0975-8887 },
pages = { 1-4 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume138/number5/24372-2016908824/ },
doi = { 10.5120/ijca2016908824 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:38:49.902877+05:30
%A Tanvi Nagariya
%A Braj Bihari Soni
%T A Survey Paper on Implementing MTCMOS Technique in Full Subtractor Circuit
%J International Journal of Computer Applications
%@ 0975-8887
%V 138
%N 5
%P 1-4
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents the study and survey analysis of Full Subtractor circuit on implementing the MTCMOS technique. Full Subtractor is a combinational circuit that performs subtraction and results in difference and borrows outputs. Implementing the MTCMOS technique on this circuit results in reduction of both leakage current and power consumption.

References
  1. Gautam M., Akashe S., “Transistor gating: reduction of leakage current and power in full subtractor circuit.” Advance Computing Conference (IACC), 2013,pp 1514-1517.
  2. Basha MM., Dr.Ramanaiah KV, Dr.Reddy PR, “Novel energy efficient 1-bit full subtractor at 65nm technology” Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015.
  3. Gautam M., Akashe S., “Reduction of leakage current and power in full subtractor using MTCMOS technique” Computer Communication and Informatics (ICCCI), 2013.
  4. Krishna S., Raghu MC and Faris S., “An efficient design of full Subtractor cell and its application in ripple borrow subtractor” International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 4, Issue 5, May 2015, pp 1473-1476.
  5. Saroja MD, Naik MR, “Reduction of leakage current and power in full subtractor using MTCMOS technique” International Journal of Review in Electronics and Communication Engineering IJRECE (2014) Vol2, Issue 4, August 2014.
  6. Rawat N., Jain R. “Power reduction approach in combinational circuit (Half and full subtractor)” International Journal of Science and Research (IJSR) Volume 3, Issue 7, July 2014.
  7. Sandana K., Sujitha K., “Static power dissipation reduction on full subtractor using MTCMOS” International Journal of Engineering & Science Research IJESR, July 2014, Vol-4, Issue-7,425-430.
Index Terms

Computer Science
Information Sciences

Keywords

Full Subtractor MTCMOS leakage current power dissipation.

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