The week's pick
Random Articles
Reseach Article
FPGA Implementation of Ring and Star NoC Architectures
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 147 - Number 13 |
| Year of Publication: 2016 |
| Authors: Ashish Valuskar, Madhu Shandilya, Arvind Rajawat |
10.5120/ijca2016911313
|
Ashish Valuskar, Madhu Shandilya, Arvind Rajawat . FPGA Implementation of Ring and Star NoC Architectures. International Journal of Computer Applications. 147, 13 ( Aug 2016), 34-36. DOI=10.5120/ijca2016911313
Abstract
Network on Chip Architecture (NoC) is considered as the next generation interconnects systems for multiprocessor systems-on-chip. Selection of the network architecture and mapping of IP nodes onto the NoC topology are two important research topics. In this paper, we proposed an implementation of a Ring and Star NoC architecture using store and forward technique.
References
- P. Guerrier, A. Greiner, “A generic architecture for on-chip packet-switched interconnections,” in Proceedings of the Automation and Test in Europe Conference and Exhibition, 2000, pp. 250-256.
- J. Duato and L. Ni S. Yalamanchili. Interconnect Networks: An Engineering Approach. In IEEE CS Press, 1998.
- Nikolay Kavaldjiev and Gerard J.M. Smit. A survey of efficient on-chip communications for SoC. In PROGRESS 2003 Embedded Systems Symposium, October 2003.
- G. Brebner and D. Levi, “Networking on chip with platform fpgas,”in Field-Programmable Technology (FPT), Proceedings. 2003 IEEE International Conference on, July 2003, pp. 13–20.
- S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg,K. Tiensyrja, and A. Hemani, “A network on chip architecture and design methodology,” in VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on. Pittsburgh, USA: IEEE Computer Society, 2002,pp. 105–112.
- W. J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” in DAC ’01: Proceedings of the 38th conference on Design automation. New York, NY, USA: ACM Press, 2001, pp.684–689.
- A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A.Zeferino, “Spin: A scalable, packet switched, on-chip micro-network,”in DATE ’03: Proceedings of the conference on Design, Automation andTest in Europe. Washington, DC, USA: IEEE Computer Society, 2003, p. 20070-20070.
- T Kogel, M. Doerper, A. Wieferink, R. Leupers, G.. Ascheid, H. Meyr,and S. Goossens, “A modular simulation framework for architecturalexploration of on-chip interconnection networks,” in CODES+ISSS ’03: Proceedings of the 1st IEEE/ACM/IFIP international conference onHardware/software codesign and system synthesis. New York, NY, USA: ACM Press, 2003, pp. 7–12.
- B.Sethuraman, “Novel Methodologies for performance and power efficient Reconfigurable Network on Chip”, IEEE International conference on Field Programmable Logic and Applications, 2006, pp.1-2, 2006.
- Eduard Fernandez Alonso,David Castellas-Rufas,Jauma Joven,Jordi Carrabina, “Survey of NoC Programming Models proposals for MPSoC”, IJCSI International Journal of Computer Science Issues, Vol. 9, Issue 2, No 3, March 2012,pp-22-32.
- Ashish Valuskar, Madhu Shandilya,Arvind Rajawat,”Analysis of Mesh Topology of NoC for Blocking and Non-blocking Technique”, IJCA Volume 70-No.14,May 2013.
Index Terms
Keywords