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Performance Analysis of Different 8x8 Bit CMOS Multiplier using 65nm Technology

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Authors:
Sona Rani, Ajay Kumar, Vikas Singla, Rakesh Singla
10.5120/ijca2016911049

Sona Rani, Ajay Kumar, Vikas Singla and Rakesh Singla. Performance Analysis of Different 8x8 Bit CMOS Multiplier using 65nm Technology. International Journal of Computer Applications 148(13):1-6, August 2016. BibTeX

@article{10.5120/ijca2016911049,
	author = {Sona Rani and Ajay Kumar and Vikas Singla and Rakesh Singla},
	title = {Performance Analysis of Different 8x8 Bit CMOS Multiplier using 65nm Technology},
	journal = {International Journal of Computer Applications},
	issue_date = {August 2016},
	volume = {148},
	number = {13},
	month = {Aug},
	year = {2016},
	issn = {0975-8887},
	pages = {1-6},
	numpages = {6},
	url = {http://www.ijcaonline.org/archives/volume148/number13/25814-2016911049},
	doi = {10.5120/ijca2016911049},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier and these multiplier are realized using bridge style full adder. All these multipliers are compared in terms of delay, power dissipation and power delay product. Simulation results show that the Array multiplier and Wallace tree multiplier using bridge style adder has less power delay product and is faster as compared to other CMOS multipliers.

References

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Keywords

CMOS, PDP, VLSI, Multiplier, Array multiplier, Wallace Tree, Braun bypass multiplier.