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Review Paper on High Speed Area Efficient Linear Convolution in Different Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 151 - Number 6 |
| Year of Publication: 2016 |
| Authors: Shubhi Shrivastava, Nashrah Fatima, Paresh Rawat |
10.5120/ijca2016911845
|
Shubhi Shrivastava, Nashrah Fatima, Paresh Rawat . Review Paper on High Speed Area Efficient Linear Convolution in Different Adder. International Journal of Computer Applications. 151, 6 ( Oct 2016), 11-14. DOI=10.5120/ijca2016911845
Abstract
On this Technical era the excessive velocity and low area of VLSI chip are very- very crucial elements. Each day quantity of transistors and different active and passive elements are drastically developing on a VLSI chip. All of the processors of the gadgets adders and multipliers are playing an essential position. An adder is a pleasing element for the designing of fast multiplier. Ultimately here want a fast adder for excessive bit edition. In this paper, they carried out of linear convolution are based on ripple carry adder and array multiplier. Offering common Boolean common sense (CBL) adder presents much less additives, less path delay and better pace compare to different present CBL adder and different adders. Right here, we're evaluating the linear convolution of different-extraordinary word length from different adders. The design and experiment may be executed by way of the useful resource of Xilinx 6.2i Spartan device circle of relatives.
References
- Jain, S. ; Saini S. “High Speed Convolution and Deconvolution algorithm (Based on Ancient Indian Vedic Mathematics) electrical engineering/electronics, computer, telecommunication and information technology (ecti-con), 2014 11th international conference on doi: 10.1109/ ecticon.2014.6839756 Publication Year: 2014 , Page(s): 1 – 5.IEEE 2014.
- Lomte, Rashmi K., and P. C. Bhaskar. ”High Speed Convolution and Deconvolution Using Urdhva Triyagbhyam.” VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on. IEEE, 2011.
- Itawadiya, Akhalesh K., et al. ”Design a DSP operations using vedic mathematics.” Communications and Signal Processing (ICCSP), 2013 International Conference on. IEEE, 2013.
- L. Sriraman, T.N. Prabakar, “Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics,” 1st Int. Conf. on Recent Advances in Information Technology, Dhanbad, India, 2012, IEEE Proc., pp. 782-787.
- Soma BhanuTej, 2012.Vedic Algorithms to develop green chips for future, International Journal of Systems, Algorithms and Applications, Volume 2, Issue ICAEM12, ISSN Online: 22772677..
- Youngjoon Kim and Lee-Sup Kim, 2001.A low power carry select adder with reduced area,IEEE International Symposium on Circuits and Systems, vol.4, pp.218-221. Tavel, P. 2007 Modeling and Simulation Design. AK Peters Ltd.
- Akhilesh Tyagi,1990.A Reduced Area Scheme for Carry- Select Adders,IEEE International Conference on Computer design, pp.255-258.
- Belle W.Y.Wei and Clark D.Thompson,1990.Area-Time Optimal Adder Design, IEEE transactions on Computers, vol.39, pp. 666675.
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