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Reseach Article

A Comparison of n-T SRAM Cell in Nanometre Regime

by Amit Namdev, Paresh Rawat
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 155 - Number 7
Year of Publication: 2016
Authors: Amit Namdev, Paresh Rawat
10.5120/ijca2016912360

Amit Namdev, Paresh Rawat . A Comparison of n-T SRAM Cell in Nanometre Regime. International Journal of Computer Applications. 155, 7 ( Dec 2016), 44-48. DOI=10.5120/ijca2016912360

@article{ 10.5120/ijca2016912360,
author = { Amit Namdev, Paresh Rawat },
title = { A Comparison of n-T SRAM Cell in Nanometre Regime },
journal = { International Journal of Computer Applications },
issue_date = { Dec 2016 },
volume = { 155 },
number = { 7 },
month = { Dec },
year = { 2016 },
issn = { 0975-8887 },
pages = { 44-48 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume155/number7/26621-2016912360/ },
doi = { 10.5120/ijca2016912360 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:00:41.540168+05:30
%A Amit Namdev
%A Paresh Rawat
%T A Comparison of n-T SRAM Cell in Nanometre Regime
%J International Journal of Computer Applications
%@ 0975-8887
%V 155
%N 7
%P 44-48
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Now a day's low power SRAMs have become a critical component of many VLSI chips. This has especially true for microprocessors, where the demanding on chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processors and the main memory. Simultaneously, power dissipation has been becoming an important factor to recognise due to the increased integration and operating speeds, as well as due to the explosive growth of battery operated applications. In this paper we have compared 4T, 6T, 7T, 8T and 9T SRAM cell at 65nm and 45nm technology by using HSPICE simulator and analyse in terms Power consumption, delay and PDP with supply voltage of 1V at 100MHz frequency.

References
  1. Y. 1. Chang, F. Lai, and C. L. Yang, "Zero-Aware Asymmetric SRAM Cell for Reducing Cache Power in Writing Zero," IEEE Transactions on Very Large Scale integration Systems, vol. 12, no. 8, pp. 827-836,2004.
  2. A. Kotabe, K. Osada, N. Kitai, M. Fujioka, S. Kamohara, M. Moniwa, S. Morita, and Y. Saitoh, "A Low-Power Four-Transistor SRAM Cell With a Stacked Vertical Poly- Silicon PMOS and a Dual-Word-Voltage Scheme," IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 870- 876,2005.
  3. L. Villa, M. Zhang, and K. Asanovic, "Dynamic zero compression for cache energy reduction," in Proceeding 33rd Annual IEEE/ACM international Symposium Micro architecture, pp. 214-220, 2000.
  4. K. Takeda et aI., "A read-static-noise-margin-free SRAM cell for low VDD and high-speed applications," IEEE Journal of Solid-State Circuits, vol. 41, no. I, pp. 113-121, 2006.
  5. J. Rabaey, A. Chandrakasan, and B. Nicolic, Digital Integrated Circuits A Design Perspective, 2nd ed. Prentice Hall, 2003.
  6. C. F. Hill, \Noise margin and noise immunity in logic circuits," Microelectronic Journal, pp. 16{21, Apr. 1968.
  7. J. Lohstroh, \Static and dynamic noise margins of logic circuits," IEEE J. Solid-State Circuits, vol. SC-14, pp. 591-598, 1979.
  8. J. Lohstroh, E. Seevinck, and J. D. Groot, \Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE J. Solid-State Circuits, vol. SC-18, pp. 803-807, 1983.
  9. C. Mead and L. Conway, Introduction to VLSI systems. Addison Wesley, 1980.
  10. Shivendra Kumar Sharma, Bhavana P.Shrivastava, “Low power and high speed 13T SRAM cell with bit-interleaving capability”, International Journals of computer Application (IJCA), vol. 141, No.11, May 2016.
  11. S. Narenda and A. Chandrakasan, Leakage in Nanometer CMOS Technology. Springer-Verlag, 2006.
  12. K. khare, R. Kar, D. Mandal, S.P. Ghosal, “Analysis of leakage current and leakage power reduction during write operation in CMOS SRAM cell” IEEE international conference on communication and signal processing, April 2014, pp. 523-527.
  13. Meng-Fan Chang, Shi-Wei Chang, Po-Wei Chou, et al., “A 130 mV SRAM with expanded write and read margins for subthreshold applications”, IEEE J. Solid-State Circuits vol. 46 , no.2, pp. 520–529 , Feb. 2011.
  14. Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsan, et al., “A single-ended disturbfree 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing”, IEEE J. Solid-State Circuits vol. 47, no. 6 , pp. 1–14, June 2012.
  15. Bo Wang, Truc Quynh Nguyen, Anh Tuan Do, Jun Zhou, , Minkyu Je, , and Tony Tae-Hyoung Kim, “Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, vol. 62, no.2, pp. 441-448, FEBRUARY 2015.
Index Terms

Computer Science
Information Sciences

Keywords

SRAM SNM Power consumption PDP.