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Reseach Article

A Comparison of n-T SRAM Cell in Nanometre Regime

by Amit Namdev, Paresh Rawat
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 155 - Number 7
Year of Publication: 2016
Authors: Amit Namdev, Paresh Rawat

Amit Namdev, Paresh Rawat . A Comparison of n-T SRAM Cell in Nanometre Regime. International Journal of Computer Applications. 155, 7 ( Dec 2016), 44-48. DOI=10.5120/ijca2016912360

@article{ 10.5120/ijca2016912360,
author = { Amit Namdev, Paresh Rawat },
title = { A Comparison of n-T SRAM Cell in Nanometre Regime },
journal = { International Journal of Computer Applications },
issue_date = { Dec 2016 },
volume = { 155 },
number = { 7 },
month = { Dec },
year = { 2016 },
issn = { 0975-8887 },
pages = { 44-48 },
numpages = {9},
url = { },
doi = { 10.5120/ijca2016912360 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-07T00:00:41.540168+05:30
%A Amit Namdev
%A Paresh Rawat
%T A Comparison of n-T SRAM Cell in Nanometre Regime
%J International Journal of Computer Applications
%@ 0975-8887
%V 155
%N 7
%P 44-48
%D 2016
%I Foundation of Computer Science (FCS), NY, USA

Now a day's low power SRAMs have become a critical component of many VLSI chips. This has especially true for microprocessors, where the demanding on chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processors and the main memory. Simultaneously, power dissipation has been becoming an important factor to recognise due to the increased integration and operating speeds, as well as due to the explosive growth of battery operated applications. In this paper we have compared 4T, 6T, 7T, 8T and 9T SRAM cell at 65nm and 45nm technology by using HSPICE simulator and analyse in terms Power consumption, delay and PDP with supply voltage of 1V at 100MHz frequency.

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Index Terms

Computer Science
Information Sciences


SRAM SNM Power consumption PDP.