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Design and Implementation of High Speed Multiplier based on Vedic Mathematics: A Review

by Pramod S. Aswale, Priyanka Nirgude, Bhakti Patil, Rohini Chaudhari
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 155 - Number 8
Year of Publication: 2016
Authors: Pramod S. Aswale, Priyanka Nirgude, Bhakti Patil, Rohini Chaudhari
10.5120/ijca2016912385

Pramod S. Aswale, Priyanka Nirgude, Bhakti Patil, Rohini Chaudhari . Design and Implementation of High Speed Multiplier based on Vedic Mathematics: A Review. International Journal of Computer Applications. 155, 8 ( Dec 2016), 1-5. DOI=10.5120/ijca2016912385

@article{ 10.5120/ijca2016912385,
author = { Pramod S. Aswale, Priyanka Nirgude, Bhakti Patil, Rohini Chaudhari },
title = { Design and Implementation of High Speed Multiplier based on Vedic Mathematics: A Review },
journal = { International Journal of Computer Applications },
issue_date = { Dec 2016 },
volume = { 155 },
number = { 8 },
month = { Dec },
year = { 2016 },
issn = { 0975-8887 },
pages = { 1-5 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume155/number8/26622-2016912385/ },
doi = { 10.5120/ijca2016912385 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:00:42.257007+05:30
%A Pramod S. Aswale
%A Priyanka Nirgude
%A Bhakti Patil
%A Rohini Chaudhari
%T Design and Implementation of High Speed Multiplier based on Vedic Mathematics: A Review
%J International Journal of Computer Applications
%@ 0975-8887
%V 155
%N 8
%P 1-5
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Multipliers being the key components of various applications and the throughput of applications depends on Arithmetic and logic units(ALU), Digital signal processing blocks and Multiplier and accumulate units. Vedic Multiplier has become highly popular as a faster method for computation and analysis.So that the latency of conventional multiplier can be reduced. Here the vedic mathematic Sutra- ‘Urdhva Tiryagbhyam’ and Nikhilum are used for efficient multiplication. The main parameters for improvement are speed, delay, hardware complexity. From this review, the conclusion regarding how well a challenge has been solved, and recognize prospective research areas that require auxiliary effort.

References
  1. G.Ganesh Kumar, V.Charishma , “Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques” International Journal of Scientific and Research Publications, Volume 2, Issue 3, March 2012 1 ISSN 2250-3153
  2. Shishir Kumar Das1 and Ankit Kumar Singh2 “Design and Implementation of Low Power Multiplier Using Vedic Multiplication Technique”
  3. 1S. S. Kerur, 1Prakash Narchi, 1Jayashree C N, 2Harish M Kittur and 3Girish V A “Implementation of Vedic Multiplier for Digital Signal Processing”.
  4. Rakesh M* M.Tech , Shilpa Rani P Asst. “Design and Implementation of High Speed 64 bit VEDIC Multiplier” International Journal of Emerging Research in Management & Technology ISSN: 2278-9359 (Volume-5, Issue-5)
  5. G.Challa Ram, Y.Rama Lakshmanna,D.Sudha Rani,K.Bala Sindhuri, “Area Efficient Modified Vedic Multiplier”, International Conference on Circuit, Power and Computing Technologies [ICCPCT]978-1-5090-1277-0/16/$31.00 2016 IEEE
  6. R. Anitha1 and Sarat Kumar Sahoo, “VLSI Implementation of Discrete Linear Convolution using Vedic Mathematics (Real and Complex Numbers)” International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 4 (2016) pp 2568-2571 Research India Publications. http://www.ripublication.com
  7. Himanshu Thapliyal Hamid, R. Arabnia, “A Time-Area- Power Efficient Multiplier and Square Architecture Based On Ancient Indian Vedic Mathematics” International Journal of Engineering Science and Computing, April 2016.
  8. Aunnaty Puri1, Utsav Malviya “Vedic Multiplication with a new Combination of Wallace Addition Structure”, International Journal of Engineering Science and Computing, April 2016 .DOI 10.4010/2016.894 ISSN 2321 3361 2016 IJESC
  9. Aniruddha Kanhe, Shishir Kumar Das and Ankit Kumar Singh “Design and Implementation of Low Power Multiplier Using Vedic Multiplication Technique”, International Journal of Computer Science and Communication Vol. 3, No. 1, January-June 2012, pp. 131-132
  10. Kaustubh Manikrao Gaikwad,Mahesh Shrikant Chavan, “Analysis of Array Multiplier and Vedic Multiplier using Xilinx” Communications on Applied Electronics (CAE) ? ISSN : 2394-4714 Foundation of Computer Science FCS, New York, USA Volume 5 ? No.1, May 2016 ? www.caeaccess.org
  11. S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A, “Implementation of Vedic Multiplier for Digital Signal Processing”, International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011Proceedings published by International Journal of Computer Applications (IJCA)
  12. Nitesh Kumar Sharma, Jigyasha Maru and M. R. Khan, “VLSI Implementation of an Approximate Multiplier using Ancient Vedic Mathematics Concept” Journal of Pure Applied and Industrial Physics, Vol.6(5), 71-82, May 2016(An International Research Journal), www.physics-journal.org
  13. Rakesh M , Shilpa Rani P “Design and Implementation of High Speed 64 bit VEDIC Multiplier”, International Journal of Emerging Research in Management & Technology ISSN: 2278-9359 (Volume-5, Issue-5) may2016
  14. K.N.Vijeyakumar1, S.Kalaiselvi2 and K. Saranya “VLSI Implementation of High Speed Area Efficient Arithmetic Unit Using Vedic Mathematics”, ICTACT JOURNAL ON MICROELECTRONICS, APRIL 2016, VOLUME: 02, ISSUE: 01
  15. Shraddha Wanjari , Dr. Sanjay Asutkar “High Performance Mac Design using Vedic Multiplier and Reversible Logic Gate”,IJSTE - International Journal of Science Technology & Engineering — Volume 2 — Issue 10 — April 2016 ISSN (online): 2349-784X
  16. Shiksha Pandey1, Deepak Kumar2, “A Fast 16x16 Vedic Multiplier Using Carry Select Adder on FPGA” International Journal of Advanced Research in Computer and Communication Engineering Vol. 5, Issue 4, April 2016
  17. Arunkumar P. Chavan, Rahul Verma , Nishanth S. Bhat “High Speed 32-bit Vedic Multiplier for DSP Applications” International Journal of Computer Applications (0975-8887) Volume 135 ?No.7, February 2016 35
  18. Suryasnata Tripathy, L B Omprakash, Sushanta K. Mandal, B S Patro “Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing”, 2015 International Conference on Communication, Information & Computing Technology (ICCICT), Jan. 16-17, Mumbai, India
  19. Bhavesh Sharma1, Amit Bakshi2, “Design and Implementation of an Efficient Single Precision Floating Point Multiplier using Vedic Multiplication”.
  20. Pranita Soni1, Swapnil Kadam2, Harish Dhurape3, Nikhil Gulavani4 “Implementation of 16x16 Bit Multiplication Algorithm by Using Vedic Mathematics Over Booth Algorithm”, IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 — pISSN: 2321- 7308
  21. Bhavesh Sharma1 , Amit Bakshi2 “Comparison of 24X24 Bit Multipliers for Various Performance Parameters”, International Journal of Research in Advent Technology (E-ISSN: 2321-9637) Special Issue 1st International Conference on Advent Trends in Engineering, Science and Technology ?ICATEST 2015?, 08 March 2015
  22. Mrs.Toni J.Billore, Prof.D.R.Rotake “FPGA implementation of high speed 8 bit Vedic Multiplier using Fast adders”, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 3, Ver. II (May-Jun. 2014), PP 54-59 e-ISSN: 2319 ? 4200, p-ISSN No. : 2319 ? 4197 www.iosrjournals.org
  23. C.Sheshavali M.Tech1, K.Niranjan kumar “Design and Implementation of Vedic Multiplier” International Journal of Engineering Research and Development e-ISSN: 2278- 067X, p-ISSN: 2278-800X, www.ijerd.com Volume 8, Issue 6 (September 2013), PP.23-28
  24. Pavan Kumar U.C.S1, Saiprasad Goud A2, A.Radhika3,“FPGA Implementation of High Speed 8- bit Vedic Multiplier Using Barrel Shifter”, International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 3, March 2013)
Index Terms

Computer Science
Information Sciences

Keywords

Vedic multiplier Nikhilum Urdhva Tiryakbhyam

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