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20 Tap Reconfigurable IIR Filter using Fully Parallel MAC Algorithm

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Rohini, Rajesh Mehra, Chandni

Rohini, Rajesh Mehra and Chandni. 20 Tap Reconfigurable IIR Filter using Fully Parallel MAC Algorithm. International Journal of Computer Applications 156(10):1-6, December 2016. BibTeX

	author = {Rohini and Rajesh Mehra and Chandni},
	title = {20 Tap Reconfigurable IIR Filter using Fully Parallel MAC Algorithm},
	journal = {International Journal of Computer Applications},
	issue_date = {December 2016},
	volume = {156},
	number = {10},
	month = {Dec},
	year = {2016},
	issn = {0975-8887},
	pages = {1-6},
	numpages = {6},
	url = {},
	doi = {10.5120/ijca2016912525},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


The paper introduces designing of MAC 20 tap IIR filter based on Field Programmable Gate Array (FPGA).The implementation is based on Multiply Add and Accumulate algorithm (MAC) unit which plays important role in many of the DSP aplications.MAC unit is used for best performance digital signal processing system. The designed filter has been synthesized on Digital Signal Processor (DSP) slice based FPGA to perform multiplier function of MAC unit. The proposed filter is implemented on two FPGA devices Xilinx’s Spartan-3E, xc3s500e-4fg320 and Vertex 2P, xc2vp30-5ff896 and compared on the basis of Direct-form I IIR and Direct–Form II IIR structure for hardware resource utilization as well as speed. The hardware result shows that the proposed low pass butterworth filter designed on spartan3E with Direct I Form 19.03% faster than that designed on vertex2p with Direct form II structure.


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IIR low pass Butterworth filter, Matlab, Xilinx, FPGA, Spatan3E, Virtex2P