Call for Paper - January 2024 Edition
IJCA solicits original research papers for the January 2024 Edition. Last date of manuscript submission is December 20, 2023. Read More

FPGA based Band Pass FIR Filter using Factored Canonic Signed Digit Technique for Satellite Application

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Roshan Lal, Rajesh Mehra, Shallu

Roshan Lal, Rajesh Mehra and Shallu. FPGA based Band Pass FIR Filter using Factored Canonic Signed Digit Technique for Satellite Application. International Journal of Computer Applications 156(3):45-49, December 2016. BibTeX

	author = {Roshan Lal and Rajesh Mehra and Shallu},
	title = {FPGA based Band Pass FIR Filter using Factored Canonic Signed Digit Technique for Satellite Application},
	journal = {International Journal of Computer Applications},
	issue_date = {December 2016},
	volume = {156},
	number = {3},
	month = {Dec},
	year = {2016},
	issn = {0975-8887},
	pages = {45-49},
	numpages = {5},
	url = {},
	doi = {10.5120/ijca2016912408},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


In this paper, an FPGA based FIR filter for Satellite Application is presented. The implementation is based on Factored Canonic signed digit (FCSD) which eliminates the use of embedded multipliers. The FIR filter has been implemented using Equiripple on an FPGA. In Equiripple, the ripples are distributed more evenly over pass band and stop band which results in a better approximation of desired frequency response can be achieved. The digital band pass filter used in satellite uplink model which is located before up converter. The uplink model used here is for C band small satellite communication system. With the performance evaluation of the equiripple filter design, it is found to be the most suitable and optimized method to meet the desired specification uplink model. An 89 tap FIR filter has been designed and simulated using 16 bit input and output precision in MATLAB environment. The behavioral simulation of VHDL model has been performed using ISE simulator. The simulated model has been synthesized using Xilinx synthesis tool (XST) on SPARTAN 3E based 3s500efg320-4 and Virtex 2P based 2vp30ff1152-5 target FPGA devices. The results depicts that FIR filter on Virtex 2P is 22.46% faster the SPARTAN 3E


  1. Kumudini Sahu, Rahul Sinha, “FIR Filter Designing using MATLAB Simulink and Xilinx system Generator,” International Research Journal of Engineering and Technology ISSN: 2277-3878, Volume: 02 Issue: 08 | Nov-2015, pp. 1608-1611.
  2. Neha Goel, Ashutosh Nandi,“Design of FIR Filter Using FCSD Representation,” IEEE International Conference on Computational Intelligence & Communication Technology978-1-4799-6023-1/15 © 2015 IEEE,pp.617-620
  3. Aye Than Mon, Zaw Min Naing, Chaw Myat New, Hla Myo Tun, “Development Of Digital Band Pass Filter And Antenna Design For C Band Small Satellite Uplink Model,” International Journal Of Scientific & Technology Research Volume 3, Issue 7, July 2014, pp. 216-222.
  4. Rohit Patel, Er. Mukesh Kumar, Prof. A.K. Jaiswal, Er. Rohini Saxena, “Design Technique of Bandpass FIR filter using Various Window Function,” IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) ISSN: 2278-8735. Volume 6, Issue 6 (Jul. - Aug. 2013), pp 52-57
  5. Kanu Priya, Rajesh Mehra, “FPGA Based Cost Efficient Fir Filter Using Factored CSD Technique,” International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-1, Issue-6, January 2013, pp. 130-133.
  6. Neha Goel, Ashutosh Nandi,“ Design of Optimized FIR Filter Using FCSD Representation” International Journal of Electrical & Electronics Engg. e-ISSN: 1694-2310 | p-ISSN: 1694-2426, Vol. 2, Spl. Issue 1 (2015)
  7. R. M. Hewlitt and E. S. Swartzlantler, Jr., “Canonical signed digit representation for FIR digital filters,” in Proc. IEEE Worksh. SignalProcess. Syst., 2000, pp. 416–426.
  8. Kuan-Hung Chen and Tzi-Dar Chiueh, “A Low-Power Digit-Based Reconfigurable FIR Filter,”IEEE Transactions On Circuits And Systems—Ii: Express Briefs, Vol. 53, No. 8, August 2006, pp. 130-133.
  9. Farzad Nekoei, Yousef S. Kavian, Otto Strobel, “Some Schemes Of Realization Digital FIR Filters On FPGA For Communication Applications,” 20th Int. Crimean Conference“Microwave & Telecommunication”, 13-17 September,Sevastopol pp. 616-619.
  10. Rajesh Mehra, Ravinder Kaur,“FPGA based Efficient Interpolator design using DALUT Algorithm,” Nabendu Chaki et al. (Eds.): NeTCoM 2010,CSCP 01, pp. 51–62, 2011.