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Hardware Accelerator for Feature Extraction based on Circle Views Signature

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Huda D. Jomma, Aziza I. Hussein, Alaa M. Hamdi

Huda D Jomma, Aziza I Hussein and Alaa M Hamdi. Hardware Accelerator for Feature Extraction based on Circle Views Signature. International Journal of Computer Applications 156(9):1-9, December 2016. BibTeX

	author = {Huda D. Jomma and Aziza I. Hussein and Alaa M. Hamdi},
	title = {Hardware Accelerator for Feature Extraction based on Circle Views Signature},
	journal = {International Journal of Computer Applications},
	issue_date = {December 2016},
	volume = {156},
	number = {9},
	month = {Dec},
	year = {2016},
	issn = {0975-8887},
	pages = {1-9},
	numpages = {9},
	url = {},
	doi = {10.5120/ijca2016912523},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


This paper presents a hardware accelerator for feature extraction based on circle views (CVs) signature suitable for shape recognition. The heavy computational and memory access needs in shape features extraction using general purpose sequential processors enforces the use of a hardware accelerator. This work presents some modifications to the original CVs signature algorithm. These modifications are intended to reduce time and space requirements for the hardware accelerator. A software version for 1NN classifier is implemented based on the modified CVs signature algorithm. This software version records 89.85% recognition rate using MPEG-7 dataset which is too close to that scored by the original CVs signature algorithm. This small reduction in performance can be ignored against the reduction in the hardware requirements and the computation time achieved. A parallel architecture for the hardware accelerator is proposed. Using 16 processing elements, the proposed hardware accelerator achieved 50.34 times speedup compared to the standard software PC implementation. A study is done to measure the effect of changing the number of processing elements on the speedup gained and the hardware components used by the proposed hardware accelerator. The proposed hardware accelerator is implemented in a field programmable gate array (FPGA) by using Verilog hardware description language.


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Feature extraction, shape recognition, real-time image processing, hardware accelerator, FPGA.