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VLSI Implementation of Split-radix FFT for High Speed Applications

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Arunkumar P. Chavan, Sowmya Nag K., Sujata Priyambada Mishra
10.5120/ijca2017912759

Arunkumar P Chavan, Sowmya Nag K. and Sujata Priyambada Mishra. VLSI Implementation of Split-radix FFT for High Speed Applications. International Journal of Computer Applications 157(7):22-26, January 2017. BibTeX

@article{10.5120/ijca2017912759,
	author = {Arunkumar P. Chavan and Sowmya Nag K. and Sujata Priyambada Mishra},
	title = {VLSI Implementation of Split-radix FFT for High Speed Applications},
	journal = {International Journal of Computer Applications},
	issue_date = {January 2017},
	volume = {157},
	number = {7},
	month = {Jan},
	year = {2017},
	issn = {0975-8887},
	pages = {22-26},
	numpages = {5},
	url = {http://www.ijcaonline.org/archives/volume157/number7/26843-2017912759},
	doi = {10.5120/ijca2017912759},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Orthogonal Frequency Division Multiplexing (OFDM) is a method of encoding digital data on multiple carrier frequencies. It is a specialized form of Frequency Division Multiplexing (FDM) where the carrier frequencies are orthogonal to each other. It finds applications in wideband digital communication, DSL internet access and power line communication. Fast Fourier transform (FFT) processing is one of the key procedures in popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures, low power consumption, high speed and reduced chip area are the primary concerns in this VLSI and signal processing domain. A 16 point FFT processor is designed using Radix-2, Radix-4 and Split-Radix algorithms and compare their performances in terms of power, delay, and Power delay product (PDP)). Vedic Multiplier and Kogge Stone adder helps in performing high speed multiplication and addition operations. The processor is implemented in RTL using Verilog HDL. Cadence environment is utilized for performing synthesis and for generating the chip layout.

References

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Keywords

Radix 2, Radix 4, Split radix, Vedic Mathematics, Urdhva Triyakhbhyam, Kogge Stone Adder