Call for Paper - January 2023 Edition
IJCA solicits original research papers for the January 2023 Edition. Last date of manuscript submission is December 20, 2022. Read More

VLSI Implementation of Split-radix FFT for High Speed Applications

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Arunkumar P. Chavan, Sowmya Nag K., Sujata Priyambada Mishra

Arunkumar P Chavan, Sowmya Nag K. and Sujata Priyambada Mishra. VLSI Implementation of Split-radix FFT for High Speed Applications. International Journal of Computer Applications 157(7):22-26, January 2017. BibTeX

	author = {Arunkumar P. Chavan and Sowmya Nag K. and Sujata Priyambada Mishra},
	title = {VLSI Implementation of Split-radix FFT for High Speed Applications},
	journal = {International Journal of Computer Applications},
	issue_date = {January 2017},
	volume = {157},
	number = {7},
	month = {Jan},
	year = {2017},
	issn = {0975-8887},
	pages = {22-26},
	numpages = {5},
	url = {},
	doi = {10.5120/ijca2017912759},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


Orthogonal Frequency Division Multiplexing (OFDM) is a method of encoding digital data on multiple carrier frequencies. It is a specialized form of Frequency Division Multiplexing (FDM) where the carrier frequencies are orthogonal to each other. It finds applications in wideband digital communication, DSL internet access and power line communication. Fast Fourier transform (FFT) processing is one of the key procedures in popular orthogonal frequency division multiplexing (OFDM) communication systems. Structured pipeline architectures, low power consumption, high speed and reduced chip area are the primary concerns in this VLSI and signal processing domain. A 16 point FFT processor is designed using Radix-2, Radix-4 and Split-Radix algorithms and compare their performances in terms of power, delay, and Power delay product (PDP)). Vedic Multiplier and Kogge Stone adder helps in performing high speed multiplication and addition operations. The processor is implemented in RTL using Verilog HDL. Cadence environment is utilized for performing synthesis and for generating the chip layout.


  1. .R.Nevin,“Application Of The Rader-Brenner Fft Algorithm To Number-Theoretic Transforms” Ieee Transactions On Acoustics, Speech, And Signal Processing Volume 25 Issue 2, 1977.
  2. Abhishek Mankar, Ansuman Diptisankar Das And N Prasad,”Fpga Implementation Of 16-Point Radix-4 Complex Fft Core Using Neda”, Students Conference On Engineering And Systems (Sces), 2013.
  3. Edwin Joseph, Rajagopal A, Karibasappa K,”Fpga Implementation Of Radix-2 Fft Processor Based On Radix-4 Cordic”, ,Nirma University International Conference On Engineering (Nuicone),2012.
  4. Saikat Kumar Shome,Abhinav Ahesh, Durgesh Kr Gupta, Srk Vadali,”Architectural Design Of A Highly Programmable Radix-2 Fft Processor With Efficient Addressing Logic”,International Conference On Devices, Circuits And Systems (Icdcs), 2012.
  5. Beard J,”An Inplace Self Recordering Fft”, Ieee International Conference On Acoustics, Speech, And Signal Processing, Icassp '78,Volume:3.
  6. Zhijian Sun, Xuemei Liu , Zhongxing Ji ,”The Design Of Radix-4 Fft By Fpga”,International Symposium On Intelligent Information Technology Application Workshops, 2008. Iitaw '08.
  7. Rashmi M J, G S Biradar, Meenakshi Patil,”Efficient Vlsi Architecture Using Dit-Fft Radix-2 And Split Radix Fft Algorithm”,International Journal For Technological Research In Engineering ,Volume 1, Issue 10, June-2014.
  8. Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim, Yong Beom Cho,”Multiplier Design Based On Ancient Indian Vedic Mathematics”, International Soc Design Conference, 2008.
  9. Mangesh B Kondalkar,Arunkumar P Chavan,P Narashimaraja ,” Improved Fault Tolerant Sparse Kogge Stone Adder“ International Journal Of Computer Applications (0975 – 8887) Volume 75– No.10, August 2013.


Radix 2, Radix 4, Split radix, Vedic Mathematics, Urdhva Triyakhbhyam, Kogge Stone Adder