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Optimized Hardware Implementation of Enhanced TRIPLE-DES using Cluster LUT and Pipelining on SPARTEN FPGA

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Amany Sarhan, Marwa Fayez, Noha Hussen
10.5120/ijca2017913608

Amany Sarhan, Marwa Fayez and Noha Hussen. Optimized Hardware Implementation of Enhanced TRIPLE-DES using Cluster LUT and Pipelining on SPARTEN FPGA. International Journal of Computer Applications 164(4):5-14, April 2017. BibTeX

@article{10.5120/ijca2017913608,
	author = {Amany Sarhan and Marwa Fayez and Noha Hussen},
	title = {Optimized Hardware Implementation of Enhanced TRIPLE-DES using Cluster LUT and Pipelining on SPARTEN FPGA},
	journal = {International Journal of Computer Applications},
	issue_date = {April 2017},
	volume = {164},
	number = {4},
	month = {Apr},
	year = {2017},
	issn = {0975-8887},
	pages = {5-14},
	numpages = {10},
	url = {http://www.ijcaonline.org/archives/volume164/number4/27469-2017913608},
	doi = {10.5120/ijca2017913608},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Due to the rapid use of Internet technology, a need for security mechanisms has appeared to protect the information. Cryptography is one of the most effective techniques used to protect and secure information. Triple Data encryption standard is a cryptography system that provides security in the commercial enterprise. A lot of research has been made over DES and Triple DES algorithms to enhance their performance. In this paper, an Enhanced Triple-DES Algorithm based on Cluster LUT (Look Up Table) and Pipelining (ETDCP) is proposed, as a modification of the Triple DES. ETDCP algorithm uses Cluster LUT in hardware implementation and uses the large embedded memories available in the SPARTAN-E FPGA as hardware designed to obtain the minimum utilized resource. Using cluster LUT diminishes the consumption power by reducing the number of registers and slice/area, which decreases the number of logic utilizations used for Spartan Xilinx FPGA. In addition, ETDCP uses pipelining techniques which will increase the processing rate. The experimental results are based on simulated and synthesized (Xilinx Spartan–E) using ModelSim 6.5 and VHDL code. The results show high throughput/area FPGA implementation. The simulation result also proves that the proposed FPGA implementation of ETDCP algorithm has better speed performance compared to previous implementations of cryptographic algorithms.

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Keywords

Cryptography, DES, FPGA, Spartan-E, Custer LUT, Pipelining.